公开(公告)号：US20050225401A1

公开(公告)日：2005-10-13

申请号：US10815219

申请日：2004-03-30

Applicant: Lewelyn D'Souza ,  Yuwen Swei

Inventor： Lewelyn D'Souza ,  Yuwen Swei

IPC: H03B1/00 ,  H03B5/24 ,  H03H11/16 ,  H03K3/011 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/099

CPC classification number: H03L7/0995 ,  H03K3/011 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026

Abstract: A design for an inverting delay component of an oscillator is disclosed, which enables the oscillator to be more tolerant of parameter variations. This increased parameter variation tolerance allows the KVCO of the oscillator to vary less between the worst case scenario (where the components of the oscillator meet minimum specifications) and the best case scenario (where the components meet the maximum specifications). This in turn means that the worst case KVCO value will be significantly smaller than in the prior art. By using a significantly smaller KVCO value, the jitter experienced at the output of the oscillator will be substantially reduced. Thus, this design enables a low-jitter oscillator to be realized.

Abstract translation: 公开了一种用于振荡器的反相延迟分量的设计，其使得振荡器能够更容忍参数变化。 这种增加的参数变化公差允许振荡器的K VCO在最坏情况（其中振荡器的组件满足最小规范）和最佳情况（其中组件满足最大值）的情况下变化较小 规格）。 这又意味着最差情况下的VCO的值将比现有技术中的显着地小。 通过使用明显较小的VCO的值，在振荡器的输出处经历的抖动将显着减小。 因此，该设计使得能够实现低抖动振荡器。

公开(公告)号：US06943608B2

公开(公告)日：2005-09-13

申请号：US10707250

申请日：2003-12-01

Applicant: Ram Kelkar

Inventor： Ram Kelkar

IPC: H03H11/26 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13

CPC classification number: H03H11/26 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00234

Abstract: A structure for a delay cell in a Voltage-Controlled Oscillators (VCO) and method for operating the delay cell. The delay cell comprises a latch and an impedance circuit (comprising resistance and capacitance elements). The impedance circuit electrically couples different nodes of the latch, a supply voltage, and ground. By adjusting the resistance of the impedance circuit, the time needed for the latch to switch states in response to the switching of an input coupled to the latch is adjusted accordingly. By choosing the appropriate nodes of the delay cell as input and output nodes of the delay cell, the delay time of the delay cell can be adjusted by adjusting the resistance of the impedance circuit. As a result, the operating frequency range of the VCO can be widened compared with prior art. Similar impedance circuits can be added to the delay cell to expand the operating frequency range of the VCO.

Abstract translation: 用于电压控制振荡器（VCO）中的延迟单元的结构以及用于操作延迟单元的方法。 延迟单元包括锁存器和阻抗电路（包括电阻和电容元件）。 阻抗电路电耦合锁存器的不同节点，电源电压和接地。 通过调整阻抗电路的电阻，相应地调整锁存器响应于耦合到锁存器的输入的切换来切换状态所需的时间。 通过选择延迟单元的适当节点作为延迟单元的输入和输出节点，可以通过调整阻抗电路的电阻来调整延迟单元的延迟时间。 结果，与现有技术相比，可以扩大VCO的工作频率范围。 类似的阻抗电路可以添加到延迟单元以扩大VCO的工作频率范围。

公开(公告)号：US20050110548A1

公开(公告)日：2005-05-26

申请号：US10835098

申请日：2004-04-29

Applicant: Masakatsu Suda ,  Satoshi Sudou ,  Toshiyuki Okayasu

Inventor： Masakatsu Suda ,  Satoshi Sudou ,  Toshiyuki Okayasu

IPC: G01R31/319 ,  G01R31/3193 ,  H03K5/13 ,  H03L7/06 ,  H03L7/081

CPC classification number: H03L7/0812 ,  G01R31/31922 ,  G01R31/31937 ,  H03K5/135 ,  H03K2005/00026 ,  H03L7/0805

Abstract: A variable delay circuit includes plural stages of first variable delay elements coupled in series for sequentially delaying a reference clock signal or a data signal, a second variable delay element coupled in parallel to the plural stages of first variable delay elements for delaying the reference clock signal, a phase comparator for comparing the phase of the reference clock signal delayed by the plural stages of first variable delay elements with the phase of the reference clock signal delayed by the second variable delay element, and a delay amount control unit for controlling the delay amount of each of the plural stages of first variable delay elements based on the comparison result of the phase comparator in order that the phase of the reference clock signal delayed by the plural stages of first variable delay elements is substantially the same as the phase of the reference clock signal delayed by the second variable delay element after predetermined cycles.

Abstract translation: 可变延迟电路包括串联耦合的多级第一可变延迟元件，用于顺序地延迟参考时钟信号或数据信号，并联耦合到多级第一可变延迟元件的第二可变延迟元件，用于延迟参考时钟信号 相位比较器，用于将由多级第一可变延迟元件延迟的参考时钟信号的相位与由第二可变延迟元件延迟的参考时钟信号的相位相比较;以及延迟量控制单元，用于控制延迟量 基于相位比较器的比较结果，使多个第一可变延迟元件中的每一个的第一可变延迟元件中的每一个基本上与第一可变延迟元件的阶段延迟的参考时钟信号的相位基本上相同 时钟信号由预定周期后的第二可变延迟元件延迟。

公开(公告)号：US20040263227A1

公开(公告)日：2004-12-30

申请号：US10876730

申请日：2004-06-25

Inventor： Michael P. Baker ,  Steven C. Meyers

IPC: H03L007/06

CPC classification number: H03L7/0995 ,  H03F2203/45362 ,  H03F2203/45466 ,  H03F2203/45644 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03L7/0812

Abstract: A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

Abstract translation: 本文提供了一种差分延迟单元，其不仅接收一对差分输入值，而且还接收一对差分控制值，用于延迟差分输入值以产生一对差分输出值。 因此，提供了一种真正差分的延迟单元，因此能够显着地提高噪声性能。 本发明的差分延迟单元还表现出围绕中心频率，恒定增益和增加的调谐范围能力的高频稳定性。 以这种方式，差分延迟单元可以分别用在PLL或DLL设计中，作为低噪声VCO或低噪声延迟线的一部分。

公开(公告)号：US06822504B2

公开(公告)日：2004-11-23

申请号：US10446076

申请日：2003-05-28

Applicant: Yoshinao Morikawa

Inventor： Yoshinao Morikawa

IPC: H01L3500

CPC classification number: H03K3/0315 ,  H03K3/011 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00039 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00208

Abstract: A correction circuit for generating a control signal for correcting a characteristic change of a first transistor includes a control signal adjusting section including a constant voltage reduction element for determining either one of a maximum voltage and a minimum voltage of the control signal and a second transistor for determining a characteristic of the control signal, a gate electrode of the second transistor receiving a prescribed voltage; and a resistor section including two types of resistor elements having resistance values of different temperature dependency characteristics from each other, the resistor elements being connected in series. The constant voltage reduction element, the second transistor, and the resistor section are connected in series between a supply terminal and a ground terminal. The control signal is output from a connection point between the control signal adjusting section and the resistor section.

Abstract translation: 用于产生用于校正第一晶体管的特性变化的控制信号的校正电路包括：控制信号调节部，包括用于确定控制信号的最大电压和最小电压中的任一个的恒定电压降低元件;以及第二晶体管， 确定所述控制信号的特性，所述第二晶体管的栅电极接收规定电压; 以及电阻器部分，其包括具有彼此不同的温度依赖特性的电阻值的两种类型的电阻器元件，电阻元件串联连接。 恒定电压降低元件，第二晶体管和电阻器部分串联连接在电源端子和接地端子之间。 控制信号从控制信号调整部和电阻部之间的连接点输出。

公开(公告)号：US20040223571A1

公开(公告)日：2004-11-11

申请号：US10366865

申请日：2003-02-14

Applicant: Rambus Inc.

Inventor： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

IPC: H04L007/00

CPC classification number: H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

Abstract translation: 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

公开(公告)号：US06768356B1

公开(公告)日：2004-07-27

申请号：US09656763

申请日：2000-09-07

Applicant: Lin Wu ,  William C. Black

Inventor： Lin Wu ,  William C. Black

IPC: H03L706

CPC classification number: H03L7/081 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0812

Abstract: In accordance with a preferred embodiment, a time-interleaved (or multi-phase) architecture is provided having individual control of a plurality of output signals or phases. The time-interleaved architecture may be implemented using a first set of delay cells such as those in a ring oscillator or a delay line device receiving overall control of its output signals by a global control signal. The global control signal may be issued by a phase-locked loop, delay-locked loop, or other like structure. A second set of delay cells is provided to further delay the output signals produced by the first set of delay cells. The second set of delay cells are controlled by individual control signals uniquely calibrated in accordance with a preferred embodiment of the invention to provide uniform (or substantially) uniform time spacing between output signals.

Abstract translation: 根据优选实施例，提供具有多个输出信号或相位的单独控制的时间交织（或多相）架构。 可以使用第一组延迟单元来实现时间交织体系结构，例如环形振荡器或延迟线设备中的延迟单元，其通过全局控制信号接收对其输出信号的总体控制。 全局控制信号可以由锁相环，延迟锁定环或其它类似结构发出。 提供第二组延迟单元以进一步延迟由第一组延迟单元产生的输出信号。 第二组延迟单元由根据本发明的优选实施例唯一校准的单独控制信号来控制，以在输出信号之间提供均匀（或基本上）均匀的时间间隔。

公开(公告)号：US20040109520A1

公开(公告)日：2004-06-10

申请号：US10249496

申请日：2003-04-15

Inventor： Ming-Hsun Hsu ,  Chien-Cheng Chang

IPC: H03D003/24

CPC classification number: H03L7/0995 ,  H03K5/133 ,  H03K5/1504 ,  H03K2005/00026 ,  H03L7/0891 ,  H03L7/18

Abstract: A multi-port network interface circuit and relative control method. The multi-port network is used for transmitting a plurality of signals to different nodes (like terminals) of a network via multiple ports of the network interface circuit. The network interface circuit triggers the transmission of the signals of the different ports with clocks of different phases, such that transition of the transmitted signals of different ports will not occur at a same time.

Abstract translation: 一种多端口网络接口电路及相对控制方法。 多端口网络用于通过网络接口电路的多个端口将多个信号发送到网络的不同节点（如终端）。 网络接口电路触发具有不同相位的时钟的不同端口的信号的传输，从而不会同时发生不同端口的发送信号的转换。

公开(公告)号：US06747500B2

公开(公告)日：2004-06-08

申请号：US10000139

申请日：2001-10-19

Applicant: Patrick H. Mawet

Inventor： Patrick H. Mawet

IPC: H03H1126

CPC classification number: H03H11/26 ,  H03K3/0231 ,  H03K5/082 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00071 ,  H03K2005/00123 ,  H03K2005/0013

Abstract: A low voltage, low power versatile and compact delay circuit for CMOS integrated circuits. The biasing circuit and comparator of the delay circuit are implemented with a relatively few simple transistor stages. This approach makes the circuit compact and allows for operation at very low supply voltages (e.g., 1.5 volts). The time delay of the delay circuit is made to depend only on passive resistive and capacitive components. The time delay is thus insensitive to fluctuations in the supply voltage, as well as fluctuations in temperature. This configuration is particularly advantageous in circuits where several timing elements need to track with one another, as they can all be formed with resistors and capacitors of the same construction. The design also makes the circuit insensitive to process parameters, as well as later environmental effects due to operating temperature, circuit aging, and the like. A common signal is used to control both a trip point voltage of a comparator and a voltage change rate of a clock ramp signal in the delay circuit, such that variations in voltage supplied to the clock during normal operation does not substantially affect the clock period.

Abstract translation: 用于CMOS集成电路的低电压，低功耗通用和紧凑的延迟电路。 延迟电路的偏置电路和比较器由相对较少的简单晶体管级实现。 这种方法使得电路紧凑，并允许在非常低的电源电压（例如，1.5伏特）下操作。 延迟电路的延时仅取决于被动电阻和电容元件。 因此，时间延迟对电源电压的波动以及温度波动不敏感。 这种配置在其中若干定时元件需要彼此跟踪的电路中是特别有利的，因为它们都可以由具有相同结构的电阻器和电容器形成。 该设计还使得电路对工艺参数不敏感，以及由于工作温度，电路老化等引起的后续环境影响。 公共信号用于控制比较器的跳变点电压和延迟电路中的时钟斜坡信号的电压变化率，使得在正常操作期间提供给时钟的电压变化基本上不影响时钟周期。

公开(公告)号：US20040048574A1

公开(公告)日：2004-03-11

申请号：US10371064

申请日：2003-02-20

Applicant: General Atomics

Inventor： Michael L. Walker ,  David S. Furuno ,  Stephan W. Gehring ,  Gerald D. Rogerson ,  Susan C. Lin

IPC: H04B015/00

CPC classification number: H04L1/08 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1508 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03K2005/00097 ,  H03K2005/00267 ,  H04B1/7176 ,  H04L5/0005 ,  H04L5/003 ,  H04L5/006

Abstract: A method and apparatus for operation in a multi-frequency band system in the presence of an interference, the method comprising the steps of: receiving signaling in a plurality of wideband frequency sub-bands, each wideband frequency sub-band having a different center frequency, wherein a bandwidth of each wideband frequency sub-band is at least 2 percent of a center frequency of the wideband frequency sub-band; detecting an interfering signal having signal energy in a portion of a respective sub-band of the wideband frequency sub-bands; deciding to discontinue use of the respective sub-band; and instructing a transmitting device transmitting the signaling to transmit subsequent signaling in any except the respective sub-band of the plurality of wideband frequency sub-bands.

Abstract translation: 一种用于在存在干扰的情况下在多频带系统中操作的方法和装置，所述方法包括以下步骤：在多个宽带频率子带中接收信令，每个宽带频率子带具有不同的中心频率 其中每个宽带频率子带的带宽是所述宽带频率子带的中心频率的至少2％; 检测在宽带频率子带的相应子带的一部分中具有信号能量的干扰信号; 决定停止使用相应的子带; 以及指示发送所述信令的发送设备，以发送除了所述多个宽带频带子带中的相应子带之外的任何信号。