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公开(公告)号：US20240030934A1
公开(公告)日：2024-01-25
申请号：US18052425
申请日：2022-11-03
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： A continuous-time delta-sigma modulator, CTDSM (400, 500, 700, 800) is described that comprises: an operational transconductance amplifier, OTA, (406, 506, 706, 806) having an input port (404, 504, 719, 739, 819, 839) configured to receive an analog input signal and an output port (408, 508, 707, 708, 807, 808); an input low pass filter network comprising at least one input resistor, R1, (402, 502, 702, 722, 802, 822) at least one first shunt capacitor, C1, (403, 503, 703, 803) and at least one feedback resistor, Rdac (410, 510, 710, 810, 730, 830) connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, (415, 515, 715, 815) in parallel to a second shunt capacitor, C2, (414, 514, 714, 814), and coupled to the output port (408, 508, 707, 708, 807, 808) of the OTA; a quantizer (413, 513, 713, 813) connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein the input and output port of the OTA connected by a third feedforward-feedback capacitor, C3, (409, 509, 709, 729, 809, 829) arranged to provide a positive feedback around the OTA.
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公开(公告)号：US11881874B2
公开(公告)日：2024-01-23
申请号：US17674788
申请日：2022-02-17
申请人： INVENSENSE, INC.
发明人： Gabriele Pelli
IPC分类号： H03M3/00 , H03F3/45 , G01C19/5712 , G01P1/00 , G01P15/08 , G01C19/5776 , G01C19/5649
CPC分类号： H03M3/376 , G01C19/5649 , G01C19/5712 , G01C19/5776 , G01P1/00 , G01P15/08 , H03F3/45 , H03M3/34 , H03M3/458 , H03M3/464 , H03F2203/45151 , H03F2203/45546
摘要： A motion sensor with sigma-delta analog-to-digital converter (ADC) having improved bias instability is presented herein. Differential outputs of a differential amplifier of the sigma-delta ADC are electrically coupled, via respective capacitances, to differential inputs of the differential amplifier. To minimize bias instability corresponding to flicker noise that has been injected into the differential inputs, the differential inputs are electrically coupled, via respective pairs of electronic switches, to feedback resistances based on a pair of switch control signals. In this regard, a first feedback resistance of the feedback resistances is electrically coupled to a first defined voltage, and a second feedback resistance of the feedback resistances is electrically coupled to a second defined reference voltage. The differential outputs are electrically coupled to differential inputs of a differential comparator of the sigma-delta ADC, and complementary outputs of the differential comparator comprise the pair of switch control signals.
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93.发明公开公开(公告)号：US20230318619A1
公开(公告)日：2023-10-05
申请号：US17713514
申请日：2022-04-05
发明人： Ilina TODOROVA , Jeffrey M. RAYNOR
IPC分类号： H03M3/00
摘要： An input stage circuit for a sigma-delta analog-to-digital converter circuit receives a digital-to-analog converter generated feedback signal and an analog current input signal to generate a difference signal applied to an integrator circuit. A single bit quantization circuit quantizes an output of the integrator circuit to generate a bit signal that is applied to an input of the digital-to-analog converter. The input stage circuit includes a switched input capacitor controlled by first and second, non-overlapping, clock signals.
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公开(公告)号：US20230283291A1
公开(公告)日：2023-09-07
申请号：US18117375
申请日：2023-03-03
发明人： Min Gyu KIM , Joseph HAMILTON , Timir NANDI , Barkat A. WANI , Praveen Kumar VENKATACHALA , Wai Laing LEE , Michael Jon WURTZ , Humberto CAMPANELLA-PINEDA
IPC分类号： H03M3/00
CPC分类号： H03M3/464 , H04R2201/003 , H04R1/08
摘要： In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.
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公开(公告)号：US11716074B2
公开(公告)日：2023-08-01
申请号：US16455992
申请日：2019-06-28
申请人： NXP B.V.
IPC分类号： H03K3/0233 , H03F3/45 , H03M3/00
CPC分类号： H03K3/0233 , H03F3/45264 , H03M3/43 , H03M3/464
摘要： A high-speed comparator circuit is provided. The circuit includes an amplifier portion, a latch portion, and a negative capacitance portion. The amplifier portion includes an input coupled to receive an analog signal and an output. The latch portion is coupled to the amplifier portion. The latch portion is configured to provide at the output a digital value based on the analog signal. The negative capacitance portion is coupled to the output. The negative capacitance portion is configured to cancel parasitic capacitance coupled at the first output.
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公开(公告)号：US20230179224A1
公开(公告)日：2023-06-08
申请号：US17538275
申请日：2021-11-30
摘要： An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.
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公开(公告)号：US20190007057A1
公开(公告)日：2019-01-03
申请号：US16104414
申请日：2018-08-17
发明人： Jae-Hoon Lee , Jong-woo Lee , Chilun Lo , Seung-hyun Oh , Jong-mi Lee
IPC分类号： H03M3/00
摘要： A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.
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公开(公告)号：US20180343013A1
公开(公告)日：2018-11-29
申请号：US15926442
申请日：2018-03-20
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal, a first summing junction configured to subtract a feedback analog signal from the input analog signal, a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.
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公开(公告)号：US10063254B1
公开(公告)日：2018-08-28
申请号：US15809974
申请日：2017-11-10
发明人： Albert E. Cosand
IPC分类号： H03M3/00
摘要： A delta sigma modulator having: an integrator that receives an input signal; a comparator that outputs a digital pulse when an output of the integrator goes beyond a threshold; a 1 bit DAC that outputs a predetermined analog signal in response to the digital pulse; and a subtractor that subtracts the analog signal from the input signal; wherein the 1-bit DAC comprises: an output MOS transistor having its gate and drain connected by default to a predetermined control voltage and to a current sink; wherein in response to the digital pulse a control circuit controllably brings the MOS transistor to a non-conductive state where any drop in voltage of its source causes the MOS transistor to conduct and, after connecting the drain of the MOS transistor away from the current sink and to an output node, pulls down the source until a predetermined charge is sent to the output node.
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公开(公告)号：US20180159550A1
公开(公告)日：2018-06-07
申请号：US15693450
申请日：2017-08-31
发明人： Xiao-Bo ZHOU
IPC分类号： H03M3/00
摘要： A sigma delta modulator includes a sigma delta modulating loop and a plurality of adjusting loops. The sigma delta modulating loop processes an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal. The first clock signal has a clock cycle. The sigma delta modulating loop has a first delay time that is the same as M times of the clock cycle. M is an integral multiple of 0.5 and is larger than 1. The adjusting loops delay the quantized output signal for second delay times, respectively, so as to generate the adjustment signal.
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