Abstract:
An electronic device is provided such as a programmable rise/fall time control circuit, for example, that delivers a continuous and near linear rising/falling slope of a control signal, with programmability that can be implemented in future CMOS image sensor devices. This device includes a programmability block for reset or transfer gate signals. The programmability block includes two inputs: an input bias current and a signal from the control bits. The programmability block further includes two similar internal circuit blocks, one for generating a fall time control signal, and one for generating a rise time control signal. Additionally the programmability block includes two outputs; a fall time control signal, and a rise time control signal. The device further includes a reset or transfer gate buffer configured as an inverter. The reset or transfer gate buffer includes three input signals: The fall time control signal and rise time control signal from the programmability block, and an INT Reset signal. Furthermore, the reset or transfer gate buffer includes an output reset or transfer gate signal. The device is configured to take an input bias current, and by controlling the transconductance of internal circuitry provide a tapered rise and fall time signal to a reset or transfer gate of a CMOS image sensor that is programmable.
Abstract:
When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.
Abstract:
The invention concerns an image-capturing apparatus and an imager. The image-capturing apparatus includes the imager in which a plurality of circuit cells are two-dimensionally aligned, and an electronic charge, photo-electronically converted from a received light and stored in each circuit cell, can be discharged from an arbitral circuit cell. The imager includes first group circuit cells to generate electronic charges corresponding to the pixels of the image including a subject, and second group circuit cells to generate electronic charges corresponding to an amount of light coming from the subject, the electronic charges further being converted to a detected value. In the imager, at least one of two operations of halting a generating-action of the electronic charges in the first group circuit cells and discharging the electronic charges from the first group circuit cells is performed, when the detected value exceeds a threshold value.
Abstract:
According to an aspect of the invention, there is provided a solid-state imaging device which discharges a signal from a photodiode in each cell in which the photodiode, a read gate reading a signal from the photodiode and a detector detecting a read signal are two-dimensionally arranged on a semiconductor substrate, then stores a signal in each photodiode, and reads a signal from each photodiode after a storage time. The device comprises a circuit performing an operation of applying to each corresponding cell a first pulse used to discharge a signal in each photodiode corresponding to one horizontal line for a plurality of horizontal lines in a first horizontal scanning period, and an operation of applying to each diode corresponding cell a second pulse used to read a signal in each photodiode corresponding to one horizontal lines for a plurality of horizontal lines in a second horizontal scanning period.
Abstract:
A semiconductor radiation imaging device includes an array of pixel cells having an array of pixel detectors which directly generate charge in response to incident radiation and a corresponding array of individually-addressable pixel circuits. Each pixel circuit is associated with a respective pixel detector for accumulating charge directly resulting from radiation incident on the pixel detector and includes threshold circuitry and charge accumulation circuitry. The threshold circuitry is configured to discard radiation hits on the pixel detector outside a predetermined threshold range, and the charge accumulation circuit is configured to accumulate charge directly resulting from a plurality of successive radiation hits on the respective pixel detector within the predetermined threshold range.
Abstract:
A CMOS sensor has unit pixels each structured by a light receiving element and three transistors, to prevent against the phenomenon of saturation shading and the reduction of dynamic range. The transition time (fall time), in switching off the voltage on a drain line shared in all pixels, is given longer than the transition time in turning of any of the reset line and the transfer line. For this reason, the transistor constituting a DRN drive buffer is made proper in its W/L ratio. Meanwhile, a control resistance or current source is inserted on a line to the GND, to make proper the operation current during driving. This reduces saturation shading amount. By making a reset transistor in a depression type, the leak current to a floating diffusion is suppressed to broaden the dynamic range.
Abstract:
The image sensor according to the present invention includes the following: a sensor unit being made up of a plurality of pixels; a scanning circuit having a dynamic logic circuit which outputs selection signals that select pixels from among the plurality of pixels in the sensor unit; and a bootstrap circuit that is placed between the scanning circuit and the sensor unit. The bootstrap circuit holds the selection signal outputted from the scanning circuit during one horizontal scanning period, and outputs, to the sensor unit, an AND signal obtained by operating a logical AND between the held selection signal and a drive signal that specifies a timing to output the AND signal to the sensor unit.
Abstract:
An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.
Abstract:
A time an ith row reset signal RSi is generated and sent out for electronic shuttering is shifted from a conventionally defined time. In this manner, it is possible to avoid overlapping between a period during which the reset signal RSi is provided and a period during which an nth pixel row is selected to perform a readout operation thereon (i.e., a period when a row select signal SLn is at “High” level). As a result, reset potentials, which could otherwise be variable depending on whether or not readout operation is being performed on any other row, can be equalized among all the rows, thus eliminating the cause of horizontal noise.
Abstract:
There is provided an image pickup apparatus comprising a plurality of pixels each including a photoelectric conversion unit which converts incident light into an electrical signal and accumulates the electrical signal, an amplifier transistor which amplifies and outputs the signal from the photoelectric conversion unit, a transfer transistor which transfers the electrical signal accumulated in the photoelectric conversion unit to the amplifier transistor, and a processing transistor which performs predetermined processing, and a control circuit which sets the signal level supplied to the control electrode of the transfer transistor in order to turn off the transfer transistor to be lower than the signal level supplied to the control electrode of the processing transistor in order to turn off the processing transistor.