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    Load multiple primitives per thread in a graphics pipeline
    104.
    发明授权
    Load multiple primitives per thread in a graphics pipeline 有权

    公开(公告)号：US12062126B2

    公开(公告)日：2024-08-13

    申请号：US17489008

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Todd Martin ,  Tad Robert Litwiller ,  Nishank Pathak ,  Randy Wayne Ramsey

    IPC: G06T15/00

    CPC classification number: G06T15/005

    Abstract: Systems, apparatuses, and methods for loading multiple primitives per thread in a graphics pipeline are disclosed. A system includes a graphics pipeline frontend with a geometry engine, shader processor input (SPI), and a plurality of compute units. The geometry engine generates primitives which are accumulated by the SPI into primitive groups. While accumulating primitives, the SPI tracks the number of vertices and primitives per group. The SPI determines wavefront boundaries based on mapping a single vertex to each thread of the wavefront while allowing more than one primitive per thread. The SPI launches wavefronts with one vertex per thread and potentially multiple primitives per thread. The compute units execute a vertex phase and a multi-cycle primitive phase for wavefronts with multiple primitives per thread.

    Memory control for data processing pipeline optimization
    105.
    发明授权
    Memory control for data processing pipeline optimization 有权

    公开(公告)号：US12056352B2

    公开(公告)日：2024-08-06

    申请号：US17955286

    申请日：2022-09-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Harris Eleftherios Gasparakis

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

    Abstract: Generating optimization instructions for data processing pipelines is described. A pipeline optimization system computes resource usage information that describes memory and compute usage metrics during execution of each stage of the data processing pipeline. The system additionally generates data storage information that describes how data output by each pipeline stage is utilized by other stages of the pipeline. The pipeline optimization system then generates the optimization instructions to control how memory operations are performed for a specific data processing pipeline during execution. In implementations, the optimization instructions cause a memory system to discard data (e.g., invalidate cache entries) without copying the discarded data to another storage location after the data is no longer needed by the pipeline. The optimization instructions alternatively or additionally control at least one of evicting, writing-back, or prefetching data to minimize latency during pipeline execution.

    GENERATING KEYS FOR A CLUSTER OF NODES IN A SINGLE SECURITY ASSOCIATION
    106.
    发明公开
    GENERATING KEYS FOR A CLUSTER OF NODES IN A SINGLE SECURITY ASSOCIATION 审中-公开

    公开(公告)号：US20240259194A1

    公开(公告)日：2024-08-01

    申请号：US18212739

    申请日：2023-06-22

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Donald Matthews, JR.

    IPC: H04L9/08 ,  H04L9/40

    CPC classification number: H04L9/0861 ,  H04L63/0428 ,  H04L9/3242

    Abstract: A computing node in a computing cluster includes at least a key generator and an encryption engine. The key generator implements a key derivation function and generates a first data encryption key based on a key derivation key. The key derivation key is a global security association encryption key shared by a plurality of nodes in the computing cluster. The first data encryption key is unique to a node pair comprising the first node and a second node of the plurality of nodes. The encryption engine encrypts a data packet using the first data encryption key.

    CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN
    107.
    发明公开
    CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN 审中-公开

    公开(公告)号：US20240258322A1

    公开(公告)日：2024-08-01

    申请号：US18401038

    申请日：2023-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0673

    Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

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