Abstract:
Disclosed is a method for producing a transparent and homogenized polymeric sol of a calcium phosphate compound, containing apatite and having excellent wettability and bioactivity, according to a sol-gel synthesis, and a method for coating the polymeric sol on a metal implant, in which the polymeric sol is coated on the metal implant and then heat-treated to form a dense coated layer strongly bonded to the metal implant. The polymeric sol is obtained by process of preparing a calcium salt solution, containing calcium ethoxide dissolved in organic acid, and a phosphate solution, containing triethyl phosphite or triethyl phosphate dissolved in the organic acid, mixing the calcium salt solution with the phosphate solution to produce a mixed solution, and aging the mixed solution.
Abstract:
A light guide member for guiding light received from a light source unit, the light source unit illuminating light toward the light guide member, the light guide member may include a plurality of first grooves on a first side of the light guide member, the first grooves extending along a first direction, and a plurality of first projections projecting from surfaces of the first grooves.
Abstract:
A light guide member for guiding light may include a first pattern on a first side of the light guide member, the first pattern may include a plurality of first features extending along a first direction, and a plurality of second features extending along a second direction, wherein the first direction crosses the second direction, the first feature has a first feature size, the second feature has a second feature size, and the first feature size may be less than the second feature size.
Abstract:
Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.
Abstract:
A light guide member for guiding light incident thereon from a light source, the light guide member including a plurality of the first grooves extending along a first direction on a first side of the light guide member, a plurality of second grooves extending along a second direction on the first side of the light guide member, the first direction may cross the second direction such that the first grooves and the second grooves may form a matrix pattern on the first side of the light guide member, wherein a polygonal shaped projection is formed between every two adjacent ones of the second grooves and a corresponding two adjacent ones of the first grooves.
Abstract:
In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
Abstract:
A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.
Abstract:
A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.
Abstract:
An array substrate includes a first line, a second line and a switching element in a pixel region defined by the first and second lines adjacent to each other. The pixel electrode is electrically connected to an electrode of the switching element through a plurality of contact holes through which the electrode of the switching element is partially exposed.
Abstract:
A heat pipe structure may include a plurality of heat pipes. Each heat pipe may include at least one ring arranged to form a passage through which a gas flows, and at least one globe arranged to form a wick, or capillary structure through which a fluid may flow. The at least one ring and the at least one globe may be arranged in a tube, which may connect a heat source and a heat dissipation part, and the fluid may be a working fluid for transferring heat.