公开(公告)号：US20070090408A1

公开(公告)日：2007-04-26

申请号：US11240487

申请日：2005-09-29

Applicant: Amlan Majumdar ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Marko Radosavljevic ,  Been-Yih Jin ,  Robert Chau

Inventor： Amlan Majumdar ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Matthew Metz ,  Marko Radosavljevic ,  Been-Yih Jin ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7854

Abstract: A field-effect transistor for a narrow-body, multiple-gate transistor such as a FinFET, tri-gate or Ω-FET is described. The corners of the channel region disposed beneath the gate are rounded n, for instance, oxidation steps, to reduce the comer effect associated with conduction initiating in the corners of the channel region.

Abstract translation: 描述了用于诸如FinFET，三栅极或者Omega-FET的窄体多栅极晶体管的场效应晶体管。 设置在栅极下方的通道区域的角部是圆形的，例如氧化步骤，以减少与沟道区域的拐角中的传导起始相关的拐角效应。

公开(公告)号：US20070069302A1

公开(公告)日：2007-03-29

申请号：US11238445

申请日：2005-09-28

Applicant: Been-Yih Jin ,  Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Justin Brask

Inventor： Been-Yih Jin ,  Robert Chau ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta ,  Mark Doczy ,  Matthew Metz ,  Justin Brask

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7851 ,  H01L29/78684

Abstract: A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.

Abstract translation: 利用对pMOS和nMOS晶体管具有单功函数的公共栅电极材料的方法，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。

公开(公告)号：US20070037372A1

公开(公告)日：2007-02-15

申请号：US11581183

申请日：2006-10-13

Applicant: Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

Inventor： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC: H01L21/3205

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

Abstract: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.

Abstract translation: 包括氮化物和填充层的牺牲栅极结构可以被金属栅电极代替。 金属栅电极可以再次被填充层覆盖的氮化物层覆盖。 氮化物和填充层的替换可以重新引入应变并提供蚀刻停止。

公开(公告)号：US20060286755A1

公开(公告)日：2006-12-21

申请号：US11154138

申请日：2005-06-15

Applicant: Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

Inventor： Justin Brask ,  Robert Chau ,  Suman Datta ,  Mark Doczy ,  Brian Doyle ,  Jack Kavalieros ,  Amlan Majumdar ,  Matthew Metz ,  Marko Radosavljevic

IPC: H01L31/119 ,  H01L31/113 ,  H01L31/062 ,  H01L29/94 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US07148099B2

公开(公告)日：2006-12-12

申请号：US10877836

申请日：2004-06-24

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L21/8338

CPC classification number: H01L21/28247 ,  H01L21/26586 ,  H01L21/28238 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可暴露于硅离子注入的垂直部分。 作为注入的结果，可以减小垂直部分的介电常数，减少边缘电容。

公开(公告)号：US07144783B2

公开(公告)日：2006-12-05

申请号：US10835791

申请日：2004-04-30

Applicant: Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew Metz ,  Robert S. Chau

Inventor： Suman Datta ,  Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew Metz ,  Robert S. Chau

IPC: H01L21/336 ,  H01L21/4763

CPC classification number: H01L29/4983 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可能暴露于还原反应的垂直部分。 作为还原反应的结果，垂直部分可以转化为金属，这增加了现有的栅电极。 在一些实施例中，在一些实施例中，去除垂直电介质部分减少了边缘电容，并且还可以有利地稍微增加向下扩散而不加热。

公开(公告)号：US07138305B2

公开(公告)日：2006-11-21

申请号：US11165724

申请日：2005-06-24

Applicant: Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott A. Hareland

Inventor： Suman Datta ,  Brian S. Doyle ,  Robert S. Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott A. Hareland

IPC: H01L21/00

CPC classification number: G11C11/412 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

公开(公告)号：US20060258072A1

公开(公告)日：2006-11-16

申请号：US11129520

申请日：2005-05-13

Applicant: Jack Kavalieros ,  Matthew Metz ,  Gilbert Dewey ,  Been-Yih Jin ,  Justin Brask ,  Suman Datta ,  Robert Chau

Inventor： Jack Kavalieros ,  Matthew Metz ,  Gilbert Dewey ,  Been-Yih Jin ,  Justin Brask ,  Suman Datta ,  Robert Chau

IPC: H01L21/8234

CPC classification number: H01L29/7391

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract translation: 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管（TFET），其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区域。

公开(公告)号：US07129182B2

公开(公告)日：2006-10-31

申请号：US10704498

申请日：2003-11-06

Applicant: Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Robert S. Chau ,  Robert B. Turkot, Jr.

Inventor： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Robert S. Chau ,  Robert B. Turkot, Jr.

IPC: H01L21/302

CPC classification number: C23F1/02 ,  H01L21/32134 ,  H01L21/823842

Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.

Abstract translation: 描述了蚀刻金属层的方法。 该方法包括在基底上形成金属层，然后将金属层的一部分暴露于包含直径超过金属层厚度的活性成分的湿式蚀刻化学物质。

公开(公告)号：US07084038B2

公开(公告)日：2006-08-01

申请号：US11210220

申请日：2005-08-22

Applicant: Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Adrian B. Sherrill ,  Markus Kuhn ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成氧化物层，并在氧化物层上形成高k电介质层。 然后将氧化物层和高k电介质层在足够的温度下退火足够的时间以产生具有渐变介电常数的栅极电介质。