公开(公告)号：US20160093631A1

公开(公告)日：2016-03-31

申请号：US14861262

申请日：2015-09-22

申请人： Tae Hwan Yun ,  Joon Hee Lee ,  Ji Young Kim

发明人： Tae Hwan Yun ,  Joon Hee Lee ,  Ji Young Kim

IPC分类号： H01L27/115 ,  H01L27/02

CPC分类号： H01L27/1157 ,  H01L21/8221 ,  H01L21/8229 ,  H01L27/11582

摘要： A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions.

摘要翻译： 存储器件包括其上具有共同源极区的衬底，沿着衬底的表面延伸的公共源极线，以及分别与公共源极区域接触的通道结构以及在公共源极线之间远离衬底的表面延伸的沟道结构。 公共源极线限定其间的存储器件的单元。 存储器件还包括具有层间绝缘层和沿通道结构的侧壁交替层叠的导电电极层的电极堆叠结构。 导电电极层限定存储器件的选择晶体管和存储单元晶体管的相应栅极。 包括牺牲层的一部分的隔离绝缘层设置在堆叠结构中的相邻的层间绝缘层之间。 隔离绝缘层将堆叠结构中的至少一个导电电极层分成电分离部分。

公开(公告)号：US20150318296A1

公开(公告)日：2015-11-05

申请号：US14702038

申请日：2015-05-01

申请人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

发明人： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

IPC分类号： H01L27/115 ,  H01L49/02

CPC分类号： H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/91

摘要： Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

摘要翻译： 提供了一种垂直非易失性存储器件，其中构成外围电路区域的电容器形成为垂直型，使得与平面电容器相比，整个器件中的电容器占据的面积可以减小。 因此，非易失性存储器件可以高度集成并具有高容量。 该装置包括具有单元区域和外围电路区域的基板，包括形成在单元区域中的多个垂直存储单元的存储单元串和形成为沿垂直于基板的第一方向穿透垂直存储单元的通道孔， 形成在基板上的外围电路区域中的与存储单元串的上表面基本相同的绝缘层，以及形成在外围电路区域上的多个电容器电极，以穿透绝缘层的至少一部分 第一方向，多个电容器电极平行于通道孔延伸。 多个电容器电极在与基板平行的第二方向上彼此间隔开，并且绝缘层插入在多个电容器电极中的一对相邻的电容器电极之间。

公开(公告)号：US20140284695A1

公开(公告)日：2014-09-25

申请号：US14151288

申请日：2014-01-09

申请人： Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

发明人： Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

IPC分类号： H01L29/792

CPC分类号： H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

摘要翻译： 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。

公开(公告)号：US08791483B2

公开(公告)日：2014-07-29

申请号：US13077254

申请日：2011-03-31

申请人： Kyung Hee Ye ,  Chang Youn Kim ,  Jin Cheol Shin ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim

发明人： Kyung Hee Ye ,  Chang Youn Kim ,  Jin Cheol Shin ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim

IPC分类号： H01L33/00

CPC分类号： H01L33/46 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/22 ,  H01L33/24 ,  H01L33/387 ,  H01L33/42 ,  H01L33/44

摘要： A high-efficiency light emitting diode including: a semiconductor stack positioned on a support substrate, including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; an insulating layer disposed in an opening that divides the p-type compound semiconductor layer and active layer; a transparent electrode layer disposed on the insulating layer and the p-type compound semiconductor layer; a reflective insulating layer covering the transparent electrode layer, to reflect light from the active layer away from the support substrate; a p-electrode covering the reflective insulating layer; and an n-electrode is formed on top of the n-type compound semiconductor layer. The p-electrode is electrically connected to the transparent electrode layer through the insulating layer.

摘要翻译： 一种高效率发光二极管，包括：位于支撑基板上的半导体堆叠，包括p型化合物半导体层，有源层和n型化合物半导体层; 设置在分隔所述p型化合物半导体层和有源层的开口中的绝缘层; 设置在绝缘层和p型化合物半导体层上的透明电极层; 覆盖所述透明电极层的反射绝缘层，以将来自所述有源层的光反射离开所述支撑基板; 覆盖反射绝缘层的p电极; 并且在n型化合物半导体层的顶部上形成n电极。 p电极通过绝缘层与透明电极层电连接。

公开(公告)号：US08618565B2

公开(公告)日：2013-12-31

申请号：US12986774

申请日：2011-01-07

申请人： Chang Youn Kim ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim

发明人： Chang Youn Kim ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim

IPC分类号： H01L33/00

CPC分类号： H01L33/22 ,  H01L33/20 ,  H01L33/382

摘要： Provided is a high-efficiency light emitting diode (LED) that includes: a support substrate; a semiconductor stack positioned on the support substrate, the semiconductor stack including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; a first electrode positioned between the support substrate and the semiconductor stack and in ohmic contact with the semiconductor stack; a first bonding pad positioned on a portion of the first electrode that is exposed outside of the semiconductor stack; and a second electrode positioned on the semiconductor stack. Protrusions are formed on exposed surfaces of the semiconductor stack. In addition, the second electrode may be positioned between the first electrode and the support substrate and contacted with the n-type compound semiconductor layer through openings of the semiconductor stack.

摘要翻译： 提供了一种高效率发光二极管（LED），其包括：支撑基板; 位于所述支撑基板上的半导体堆叠，所述半导体堆叠包括p型化合物半导体层，有源层和n型化合物半导体层; 位于所述支撑衬底和所述半导体堆叠之间并与所述半导体堆叠欧姆接触的第一电极; 位于所述第一电极的暴露于所述半导体叠层外部的部分上的第一焊盘; 以及位于半导体堆叠上的第二电极。 突起形成在半导体堆叠的暴露表面上。 此外，第二电极可以位于第一电极和支撑衬底之间，并且通过半导体叠层的开口与n型化合物半导体层接触。

公开(公告)号：US20130292645A1

公开(公告)日：2013-11-07

申请号：US13997873

申请日：2011-12-06

申请人： Jun Ho Yun ,  Ki Bum Nam ,  Joon Hee Lee ,  Chang Youn Kim ,  Hong Jae Yoo ,  Sung Hoon Hong

发明人： Jun Ho Yun ,  Ki Bum Nam ,  Joon Hee Lee ,  Chang Youn Kim ,  Hong Jae Yoo ,  Sung Hoon Hong

IPC分类号： H01L33/14

CPC分类号： H01L33/14 ,  H01L33/0079 ,  H01L33/22 ,  H01L33/38 ,  H01L33/405 ,  H01L33/44

摘要： Disclosed herein is a high efficiency light emitting diode. The light emitting diode includes: a semiconductor stack positioned over a support substrate; a reflective metal layer positioned between the support substrate and the semiconductor stack to ohmic-contact a p-type compound semiconductor layer of the semiconductor stack and having a groove exposing the semiconductor stack; a first electrode pad positioned on an n-type compound semiconductor layer of the semiconductor stack; an electrode extension extending from the first electrode pad and positioned over the groove region; and an upper insulating layer interposed between the first electrode pad and the semiconductor stack. In addition, the n-type compound semiconductor layer includes an n-type contact layer, and the n-type contact layer has a Si doping concentration of 5 to 7×1018/cm3 and a thickness in the range of 5 to 10 um.

摘要翻译： 本文公开了一种高效率发光二极管。 发光二极管包括：位于支撑衬底上的半导体堆叠; 反射金属层，位于所述支撑基板和所述半导体堆叠之间，以与所述半导体堆叠的p型化合物半导体层欧姆接触并具有暴露所述半导体叠层的沟槽; 位于所述半导体叠层的n型化合物半导体层上的第一电极焊盘; 电极延伸部，其从所述第一电极焊盘延伸并定位在所述沟槽区域上; 以及介于所述第一电极焊盘和所述半导体堆叠之间的上绝缘层。 此外，n型化合物半导体层包括n型接触层，n型接触层的Si掺杂浓度为5〜7×1018 / cm3，厚度为5〜10μm。

公开(公告)号：US08575680B2

公开(公告)日：2013-11-05

申请号：US13564117

申请日：2012-08-01

申请人： Yoo-Cheol Shin ,  Joon-Hee Lee

发明人： Yoo-Cheol Shin ,  Joon-Hee Lee

IPC分类号： H01L29/788

CPC分类号： H01L21/764 ,  H01L27/11521

摘要： A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.

摘要翻译： 半导体器件包括在衬底的有源区上的隧道绝缘层，隧道绝缘层上的浮动栅电极，衬底内的隔离沟槽，隔离沟槽限定有源区，使隧道绝缘层隔开，并隔离浮置栅电极 。 隔离沟槽的底部直接与衬底接触。 半导体器件还包括浮置栅电极上的下绝缘层，以及堆叠在下绝缘层上的中间绝缘层，上绝缘层和控制栅电极。 下绝缘层被配置为气密地密封隔离沟槽的顶部以限定和直接邻接隔离沟槽内的气隙。

公开(公告)号：US08406298B2

公开(公告)日：2013-03-26

申请号：US11643799

申请日：2006-12-22

申请人： Jun-hae Choi ,  Seung-gi Chang ,  Chang-yeul Kwon ,  Joon-hee Lee ,  Ju-han Lee

发明人： Jun-hae Choi ,  Seung-gi Chang ,  Chang-yeul Kwon ,  Joon-hee Lee ,  Ju-han Lee

IPC分类号： H04N11/02 ,  H04J1/16

CPC分类号： H04B3/54 ,  H04B2203/5408 ,  H04L69/22

摘要： A method and apparatus to efficiently transmit data. The method and apparatus effectively aggregate data and transmit the data in a high-speed power line communication (PLC) network. The method of transmitting the data includes combining each of at least one or more data units transferred from an upper layer, with a field to indicate attribute information of the data unit, dividing the combined data units and fields into frame blocks of an identical size, and aggregating the divided frame blocks and transferring the aggregated frame blocks as one frame to a PHY layer. In this way, data units of a variety of types and sizes transferred from the upper layer are aggregated and transmitted as the one frame.

摘要翻译： 一种有效传输数据的方法和装置。 该方法和设备在高速电力线通信（PLC）网络中有效地聚合数据并传输数据。 发送数据的方法包括将从上层传送的至少一个或多个数据单元中的每一个与用于指示数据单元的属性信息的字段组合，将组合的数据单元和字段分成相同大小的帧块， 并且聚合分割的帧块并将聚合的帧块作为一个帧传送到PHY层。 以这种方式，从上层传送的各种类型和大小的数据单元被聚合并作为一帧传送。

公开(公告)号：US20130068500A1

公开(公告)日：2013-03-21

申请号：US13701675

申请日：2011-06-03

申请人： Sun-Joo Park ,  Joon-Hee Lee ,  Dong-Jin Seo

发明人： Sun-Joo Park ,  Joon-Hee Lee ,  Dong-Jin Seo

IPC分类号： H01B3/30

CPC分类号： H01B3/306 ,  H01B3/305 ,  H01B7/0216 ,  H01B7/292

摘要： The present invention provides an insulated wire having a conductor and at least two insulating coating layers formed surrounding the conductor, wherein the insulating coating layers comprises the outermost layer thereof, which has a thickness in the range of 20 to 50% based on the total thickness of the insulating coating layers and comprises a polyimide resin; and a base insulating coating layer in contact with the conductor, which has a thickness in a range of 50 to 80% based on the total thickness of the insulating coating layers and comprises a polyamide-imide resin having an adhesion-improving agent. The insulated wire of the present invention has insulating coating layers having superior coating adhesion as well as good heat-resistance.

摘要翻译： 本发明提供了一种绝缘电线，其具有导体和围绕导体形成的至少两个绝缘涂层，其中绝缘涂层包括其最外层，其厚度基于总厚度为20至50％ 的绝缘涂层，并且包括聚酰亚胺树脂; 以及与所述导体接触的基底绝缘涂层，其基于所述绝缘涂层的总厚度具有在50至80％的范围内的厚度，并且包括具有粘合性改进剂的聚酰胺 - 酰亚胺树脂。 本发明的绝缘电线具有优异的涂层密合性和良好的耐热性的绝缘涂层。

公开(公告)号：US20120247806A1

公开(公告)日：2012-10-04

申请号：US13432433

申请日：2012-03-28

申请人： Hyung-Sam CHOI ,  Joon-Hee Lee ,  Ki-Hong Park ,  Sun-Joo Park

发明人： Hyung-Sam CHOI ,  Joon-Hee Lee ,  Ki-Hong Park ,  Sun-Joo Park

IPC分类号： H01B3/30 ,  C08K5/544 ,  B82Y30/00

CPC分类号： C08G73/14 ,  C09D7/62 ,  C09D7/67 ,  C09D7/68 ,  C09D179/08 ,  C08K3/36

摘要： Disclosed is an insulating varnish composition including polyamideimide resin and 1 to 40 parts by weight of surface-treated silica in a sol state per 100 parts by weight of the polyamideimide resin. An insulated layer formed using the insulating varnish composition may have excellent corona discharge resistance, thereby preventing the insulation breakdown.

摘要翻译： 公开了一种绝缘漆组合物，其包含聚酰胺酰亚胺树脂和1至40重量份的溶胶状态的表面处理二氧化硅，每100重量份的聚酰胺酰亚胺树脂。 使用绝缘漆组合物形成的绝缘层可以具有优异的电晕放电电阻，从而防止绝缘击穿。