公开(公告)号：US20100025857A1

公开(公告)日：2010-02-04

申请号：US12181467

申请日：2008-07-29

申请人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

发明人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC分类号： H01L23/48 ,  G06F9/45

CPC分类号： H01L21/76898 ,  H01L21/76838 ,  H01L21/7684

摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.

摘要翻译： 具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

公开(公告)号：US07655495B2

公开(公告)日：2010-02-02

申请号：US11623977

申请日：2007-01-17

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

公开(公告)号：US20090316313A1

公开(公告)日：2009-12-24

申请号：US12144084

申请日：2008-06-23

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC分类号： H02H9/00 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

摘要翻译： 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。 每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。 所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。

公开(公告)号：US20090288869A1

公开(公告)日：2009-11-26

申请号：US12427775

申请日：2009-04-22

申请人： Felix P. Anderson ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Felix P. Anderson ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H05K1/02 ,  H01R43/16

CPC分类号： H01L23/5283 ,  H01G4/232 ,  H01G4/306 ,  H01G4/33 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/49204 ,  H01L2924/00

摘要： A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure.

摘要翻译： 公开了一种用于减小集成电路中的高场强的区域的方法。 在一个实施例中，该方法包括在集成电路的第一互连层中形成第一曲线布线结构。 可以在集成电路的第二互连层中形成第二曲线布线结构，使得第一和第二曲线布线结构基本上垂直对齐。 然后可以将第一曲线性布线结构电连接到第二曲线布线结构。

公开(公告)号：US07459389B2

公开(公告)日：2008-12-02

申请号：US11391050

申请日：2006-03-28

申请人： Anthony K. Stamper

发明人： Anthony K. Stamper

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

摘要： A method of forming a semiconductor device. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

摘要翻译： 一种形成半导体器件的方法。 沉积第一和第二介电材料的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。 在电介质材料的交替层中形成第一个特征。 选择性地蚀刻电介质材料的交替层以去除具有第一介电材料的每个层中的第一介电材料的至少一部分，并使第二介电材料基本上未被蚀刻。

公开(公告)号：US20080173981A1

公开(公告)日：2008-07-24

申请号：US11624712

申请日：2007-01-19

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.

摘要翻译： 具有一个或多个垂直板电容器的集成电路（IC）芯片，每个垂直板电容器连接到IC芯片上的电路和制造芯片电容器的方法。 垂直板电容器在电路层上形成有底板图案（例如，镶嵌铜），以及与基板图案连接并基本相同的至少一个上板层（例如双镶嵌铜）。 一对电容器板由板层和底板形成。 垂直对电容器板之间的电容电介质至少部分地是高k电介质。

公开(公告)号：US20080146040A1

公开(公告)日：2008-06-19

申请号：US12041782

申请日：2008-03-04

申请人： Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H01L21/31

CPC分类号： C23C16/04 ,  C23C16/513 ,  H01J37/32366

摘要： A method and an apparatus for performing the method. The method includes: (a) providing an apparatus, wherein the apparatus comprises (i) a chamber, (ii) a plasma device being in and coupled to the chamber, (iii) a shower head being in and coupled to the chamber, and (iv) a chuck being in and coupled to the chamber; (b) placing the substrate on the chuck; (c) using the plasma device to receive a plasma device gas and generate a plasma; (d) directing the plasma at a pre-specified area on the substrate; and (e) using the shower head to receive and distribute a shower head gas in the chamber, wherein the plasma device gas and the shower head gas are selected such that the plasma and the shower head gas when mixed with each other result in a chemical reaction that forms a film at the pre-specified area on the substrate.

摘要翻译： 一种用于执行该方法的方法和装置。 该方法包括：（a）提供一种设备，其中所述设备包括（i）室，（ii）位于室中并耦合到所述室的等离子体设备，（iii）淋浴喷头位于并联接到所述室，以及 （iv）卡盘位于并联接到所述腔室; （b）将基板放置在卡盘上; （c）使用等离子体装置接收等离子体装置气体并产生等离子体; （d）将等离子体引导到基板上的预定区域; 以及（e）使用所述淋浴头来接收和分配所述腔室中的淋浴头气体，其中所述等离子体装置气体和所述喷淋头气体被选择为使得当彼此混合时所述等离子体和所述淋浴头气体产生化学物质 在基板上的预定区域形成膜的反应。

公开(公告)号：US07382055B2

公开(公告)日：2008-06-03

申请号：US11846595

申请日：2007-08-29

申请人： Eric M. Coker ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Matthew D. Moon ,  Anthony K. Stamper

发明人： Eric M. Coker ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Matthew D. Moon ,  Anthony K. Stamper

IPC分类号： H01L29/40

CPC分类号： H01L27/016

摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

公开(公告)号：US07288475B2

公开(公告)日：2007-10-30

申请号：US11558959

申请日：2006-11-13

申请人： Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/02167 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

公开(公告)号：US07230336B2

公开(公告)日：2007-06-12

申请号：US10338624

申请日：2003-01-07

申请人： Charlotte D Adams ,  Anthony K. Stamper

发明人： Charlotte D Adams ,  Anthony K. Stamper

IPC分类号： H01L29/40

CPC分类号： H01L21/76808 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/7684

摘要： A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

摘要翻译： 一种用于制造电接触镶嵌钨布线层的双镶嵌铜互连的方法和结构。 该方法在半导体衬底上形成第一层，在第一层上形成氮化硅层，在氮化硅层上形成二氧化硅层。 第一层包括由绝缘介电材料隔开的镶嵌钨互连区域。 通过蚀刻通过二氧化硅和氮化硅层的两个接触槽来暴露镶嵌钨互连区域，并且通过在两个接触槽之间蚀刻二氧化硅层的顶部部分来形成连续空间。 二氧化硅层的缩小部分保留在两个接触槽之间。 连续的空间填充有镶嵌铜。 所得到的双镶嵌铜互连件电接触暴露的镶嵌钨互连区域。