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    Dual damascene copper interconnect to a damascene tungsten wiring level
    1.
    发明授权
    Dual damascene copper interconnect to a damascene tungsten wiring level 有权
    双镶嵌铜互连到镶嵌钨布线层

    公开(公告)号：US07230336B2

    公开(公告)日：2007-06-12

    申请号：US10338624

    申请日：2003-01-07

    申请人： Charlotte D Adams ,  Anthony K. Stamper

    发明人： Charlotte D Adams ,  Anthony K. Stamper

    IPC分类号： H01L29/40

    CPC分类号： H01L21/76808 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/7684

    摘要： A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

    摘要翻译： 一种用于制造电接触镶嵌钨布线层的双镶嵌铜互连的方法和结构。 该方法在半导体衬底上形成第一层，在第一层上形成氮化硅层，在氮化硅层上形成二氧化硅层。 第一层包括由绝缘介电材料隔开的镶嵌钨互连区域。 通过蚀刻通过二氧化硅和氮化硅层的两个接触槽来暴露镶嵌钨互连区域，并且通过在两个接触槽之间蚀刻二氧化硅层的顶部部分来形成连续空间。 二氧化硅层的缩小部分保留在两个接触槽之间。 连续的空间填充有镶嵌铜。 所得到的双镶嵌铜互连件电接触暴露的镶嵌钨互连区域。

    Dual damascene copper interconnect to a damascene tungsten wiring level
    2.
    发明授权
    Dual damascene copper interconnect to a damascene tungsten wiring level 有权
    双镶嵌铜互连到镶嵌钨布线层

    公开(公告)号：US06566242B1

    公开(公告)日：2003-05-20

    申请号：US09816977

    申请日：2001-03-23

    申请人： Charlotte D. Adams ,  Anthony K. Stamper

    发明人： Charlotte D. Adams ,  Anthony K. Stamper

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/7684

    摘要： A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

    摘要翻译： 一种用于制造电接触镶嵌钨布线层的双镶嵌铜互连的方法和结构。 该方法在半导体衬底上形成第一层，在第一层上形成氮化硅层，在氮化硅层上形成二氧化硅层。 第一层包括由绝缘介电材料隔开的镶嵌钨互连区域。 通过蚀刻通过二氧化硅和氮化硅层的两个接触槽来暴露镶嵌钨互连区域，并且通过在两个接触槽之间蚀刻二氧化硅层的顶部部分来形成连续空间。 二氧化硅层的缩小部分保留在两个接触槽之间。 连续的空间填充有镶嵌铜。 所得到的双镶嵌铜互连件电接触暴露的镶嵌钨互连区域。

    Test structure and calibration method
    6.
    发明授权
    Test structure and calibration method 有权
    测试结构和校准方法

    公开(公告)号：US08829518B2

    公开(公告)日：2014-09-09

    申请号：US13231516

    申请日：2011-09-13

    申请人： Jeffrey C. Maling ,  Anthony K. Stamper ,  Eric J. White

    发明人： Jeffrey C. Maling ,  Anthony K. Stamper ,  Eric J. White

    IPC分类号： H01L29/10

    CPC分类号： B81C99/004

    摘要： A test structure for measuring a Micro-Electro-Mechanical System (MEMS) cavity height structure and calibration method. The method includes forming a sacrificial cavity material over a plurality of electrodes and forming an opening into the sacrificial cavity material. The method further includes forming a transparent or substantially transparent material in the opening to form a transparent or substantially transparent window. The method further includes tuning a thickness of the sacrificial cavity material based on measurements obtained through the transparent or substantially transparent window.

    摘要翻译： 用于测量微机电系统（MEMS）腔体高度结构和校准方法的测试结构。 该方法包括在多个电极上形成牺牲腔材料并在牺牲腔材料中形成开口。 该方法还包括在开口中形成透明或基本上透明的材料以形成透明或基本上透明的窗口。 该方法还包括基于通过透明或基本上透明的窗口获得的测量值调整牺牲腔材料的厚度。

    Interconnect structures and design structures for a radiofrequency integrated circuit
    7.
    发明授权
    Interconnect structures and design structures for a radiofrequency integrated circuit 有权
    射频集成电路的互连结构和设计结构

    公开(公告)号：US08791545B2

    公开(公告)日：2014-07-29

    申请号：US13560446

    申请日：2012-07-27

    申请人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： Timothy J. Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01L21/02

    CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/016 ,  H01L28/20 ,  H01L28/40

    摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

    摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。

    Wiring structure and method of forming the structure
    8.
    发明授权
    Wiring structure and method of forming the structure 有权
    布线结构及形成方法

    公开(公告)号：US08569888B2

    公开(公告)日：2013-10-29

    申请号：US13114079

    申请日：2011-05-24

    申请人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    发明人： Fen Chen ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Timothy D. Sullivan

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

    摘要翻译： 公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。 较厚的上部位于布线结构和相邻电介质材料之间的接合处。 较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。 较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。