公开(公告)号：US09761724B2

公开(公告)日：2017-09-12

申请号：US15182343

申请日：2016-06-14

Applicant: Intel Corporation

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L21/84 ,  H01L29/04 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US09564490B2

公开(公告)日：2017-02-07

申请号：US14985282

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L29/772 ,  H01L29/12 ,  H01L29/15 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/205 ,  H01L29/207

CPC classification number: H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap.

Abstract translation: 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例，其可以包括形成调制掺杂异质结构，包括形成具有第一带隙的有源部分并形成具有第二带隙的δ掺杂部分。

公开(公告)号：US20160315153A1

公开(公告)日：2016-10-27

申请号：US15197615

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L29/06 ,  H01L29/20 ,  H01L27/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L23/66 ,  H01L29/04 ,  H01L29/205

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20160233336A1

公开(公告)日：2016-08-11

申请号：US15045666

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/7848 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762

Abstract: Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

公开(公告)号：US20160079359A1

公开(公告)日：2016-03-17

申请号：US14946718

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283 ,  H01L21/324 ,  H01L21/225 ,  H01L21/3213 ,  H01L21/31 ,  H01L21/311 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20150236100A1

公开(公告)日：2015-08-20

申请号：US14702608

申请日：2015-05-01

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/201 ,  H01L29/207 ,  H01L29/78 ,  H01L29/51 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.