公开(公告)号：US20190066804A1

公开(公告)日：2019-02-28

申请号：US16043259

申请日：2018-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C29/02 ,  G06F11/07 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/073 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

公开(公告)号：US20180322922A1

公开(公告)日：2018-11-08

申请号：US16019650

申请日：2018-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  G11C29/52

CPC classification number: G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

公开(公告)号：US10062441B1

公开(公告)日：2018-08-28

申请号：US15692154

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/073 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24

Abstract: Methods of operating a memory include determining a respective raw data value for each memory cell of a plurality of memory cells; determining the numbers of memory cells of a first subset of the plurality of memory cells having each raw data value as their respective raw data value; determining a respective raw data values representative of transition between each pair of adjacent data states responsive to the determined numbers of memory cells of the first subset of the plurality of memory cells for each raw data value; and determining a respective data state of the plurality of data states for each memory cell of a second subset of the plurality of memory cells responsive to its respective raw data value and to the determined raw data values representative of the transitions between adjacent data states.

公开(公告)号：US10049038B2

公开(公告)日：2018-08-14

申请号：US14809959

申请日：2015-07-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Pasquale Conenna

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F12/0875 ,  G06F13/16 ,  G11C16/10

Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.

公开(公告)号：US09965208B1

公开(公告)日：2018-05-08

申请号：US13774688

申请日：2013-02-22

Applicant: Micron Technology, Inc.

Inventor： Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge

IPC: G06F3/06 ,  G06F11/22 ,  G06F11/10

CPC classification number: G06F3/0634 ,  G06F3/0626 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1064 ,  G06F11/2263

Abstract: Configurable operating mode memory devices are disclosed. In at least one embodiment, a memory device is configurable into one or more operating modes. An array of memory cells can be allocated into one or more partitions where each partition is associated only with a particular mode of operation. In at least one other embodiment, a memory device is configured to store user data in a portion of a memory array and to store data corresponding to a logical function associated with a different operating mode of the memory device in a different portion of the memory array.

公开(公告)号：US20160371335A1

公开(公告)日：2016-12-22

申请号：US15253965

申请日：2016-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Giulio G. Marotta ,  Marco-Domenico Tiburzi ,  Tommaso Vali ,  Frankie F. Roohparvar ,  Agostino Macerola

IPC: G06F17/30 ,  G11C15/04 ,  G06F12/0802 ,  G11C29/50 ,  G06F7/20

CPC classification number: G06F17/30495 ,  G06F3/0628 ,  G06F7/20 ,  G06F12/0802 ,  G06F2212/1021 ,  G06F2212/608 ,  G11C7/1006 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/06 ,  G11C29/50004 ,  G11C29/50016

Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Abstract translation: 用于促进图案匹配并具有存储器单元阵列的存储器件，用于存储关键字的表示的多个键寄存器和多个复用器，多个多路复用器的每个复用器用于从一个或多个多路复用器中选择一个位的表示 多个密钥寄存器的密钥寄存器与存储在存储器单元阵列中的数据进行比较。

公开(公告)号：US09405859B1

公开(公告)日：2016-08-02

申请号：US13864605

申请日：2013-04-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C11/34 ,  G11C16/04 ,  G06F17/30 ,  G11C15/00 ,  G06F12/02

CPC classification number: G06F17/30982 ,  G06F12/0246 ,  G11C7/1006 ,  G11C15/00 ,  G11C16/0483

Abstract: Methods for storing a feature vector, as well as related comparison units and systems. One such method involves programming a string of memory cells of memory to store do not care data as at least a portion of a value of an attribute of the feature vector.

Abstract translation: 存储特征向量的方法，以及相关的比较单元和系统。 一种这样的方法涉及编程存储器的一串存储器单元以存储不关心数据作为特征向量的属性的值的至少一部分。

公开(公告)号：US09343155B1

公开(公告)日：2016-05-17

申请号：US13774636

申请日：2013-02-22

Applicant: Micron Technology, Inc.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: Methods for programming, methods for operating, and memories are disclosed. One such method for programming includes programming a group of memory cells such that a series string of memory cells of the group of memory cells is programmed to provide a logical function responsive to an input minterm whose variables are coupled to respective, associated memory cells.

Abstract translation: 公开了编程方法，操作方法和存储器。 用于编程的一种这样的方法包括对一组存储器单元进行编程，使得存储器单元组的一系列存储器单元被编程为响应于其变量耦合到相应的存储单元的输入minter来提供逻辑功能。

公开(公告)号：US09128894B2

公开(公告)日：2015-09-08

申请号：US14170728

申请日：2014-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Pasquale Conenna

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F12/0875 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/202 ,  G06F2212/452 ,  G11C16/10

Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.

Abstract translation: 总线控制器具有置换器，耦合到置换器的算术逻辑单元和选择性地耦合到置换器和算术逻辑单元的替换器。

公开(公告)号：US20140133226A1

公开(公告)日：2014-05-15

申请号：US14159041

申请日：2014-01-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giulio Marotta ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C2211/5641

Abstract: Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.

Abstract translation: 公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。 在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。 当内存使用量低时，使用SLC模式。 当内存使用率高时，使用MLC模式。 动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。