公开(公告)号：US20240038730A1

公开(公告)日：2024-02-01

申请号：US18478821

申请日：2023-09-29

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/1207

Abstract: A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

公开(公告)号：US11889693B2

公开(公告)日：2024-01-30

申请号：US17366471

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Srikant Jayanti ,  Fatma Arzum Simsek-Ege ,  Pavan Kumar Reddy Aella

IPC: H10B43/27 ,  H10B41/27 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L21/3213 ,  H10B99/00 ,  H01L29/04 ,  H01L29/16 ,  H01L29/51 ,  H01L29/792 ,  H10B41/20

CPC classification number: H10B43/27 ,  H01L21/022 ,  H01L21/0234 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32134 ,  H01L29/04 ,  H01L29/16 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H10B41/27 ,  H10B99/00 ,  H01L29/7926 ,  H10B41/20

Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.

公开(公告)号：US11862668B2

公开(公告)日：2024-01-02

申请号：US17366557

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

IPC: H01L29/04 ,  H01L29/10 ,  H10B12/00 ,  H10B53/30

CPC classification number: H01L29/04 ,  H01L29/1033 ,  H10B12/00 ,  H10B53/30

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US20230411352A1

公开(公告)日：2023-12-21

申请号：US17804258

申请日：2022-05-26

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H01L25/065 ,  H01L23/00 ,  H01L27/108 ,  H01L27/11553 ,  H01L27/11582

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L2224/08146 ,  H01L27/11553 ,  H01L27/11582 ,  H01L27/10814

Abstract: A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure vertically neighboring the first microelectronic device structure, and a third microelectronic device structure vertically neighboring the second microelectronic device structure. The first microelectronic device structure comprises a first memory array region and the third microelectronic device structure comprises a second memory array region. The second microelectronic device structure comprises a control logic region comprising a first sub word liner driver region comprising transistor structures in electrical communication with structures of the first microelectronic device structure and a second sub word line driver region comprising additional transistor structures in electrical communication with structures of the third microelectronic device structure. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230410040A1

公开(公告)日：2023-12-21

申请号：US18242915

申请日：2023-09-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Gitanjali T. Ghosh ,  Yixin Yan ,  Rosa M. Avila-Hernandez

IPC: G06Q10/087 ,  G06N20/00

CPC classification number: G06Q10/087 ,  G06N20/00

Abstract: Methods, apparatuses, and systems associated with inventory management are described. Examples can include receiving at a processor first signaling from a first sensor device configured to monitor the interior of a first enclosure and receiving at the processor second signaling from a second sensor device configured to monitor the interior of a second enclosure. Examples can include writing from the processor to a storage device coupled to the processor data that is based at least in part on a combination of the first and second signaling, identifying a quantity or amount of at least one item in the first enclosure and at least one item in the second enclosure, and transmitting third signaling when the quantity or amount of the at least one item in the first enclosure or the at least one item in the second enclosure is less than a threshold value.

公开(公告)号：US11842990B2

公开(公告)日：2023-12-12

申请号：US17364377

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/18 ,  H01L24/83 ,  H01L25/50 ,  H10B12/036 ,  H10B12/33 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, word lines coupled to the memory cells, and isolation material overlying the memory cells, the digit lines, and the word lines. An additional microelectronic device structure assembly comprising control logic devices and additional isolation material overlying the control logic devices is formed. The additional isolation material of the additional microelectronic device structure assembly is bonded to the isolation material of the microelectronic device structure assembly to attach the additional microelectronic device structure assembly to the microelectronic device structure assembly. The memory cells are electrically connected to at least some of the control logic devices after bonding the additional isolation material to the isolation material. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11811874B2

公开(公告)日：2023-11-07

申请号：US17719790

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Sharmila Velamur ,  Fatma Arzum Simsek-Ege ,  Shivani Srivastava ,  Marsela Pontoh ,  Lavanya Sriram

IPC: H04L67/125 ,  H04L67/00

CPC classification number: H04L67/125 ,  H04L67/34

Abstract: Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.

公开(公告)号：US11797192B2

公开(公告)日：2023-10-24

申请号：US17236183

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Carly M. Wantulok ,  Sumana Adusumilli ,  Chiara Cerafogli

IPC: G06F3/06 ,  G06N20/00

CPC classification number: G06F3/0619 ,  G06F3/067 ,  G06F3/0623 ,  G06F3/0656 ,  G06F3/0659 ,  G06N20/00

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. Data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. Data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. Data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.

公开(公告)号：US20230069570A1

公开(公告)日：2023-03-02

申请号：US17411801

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Deepti Verma ,  Shruthi Kumara Vadivel

IPC: G16H20/00 ,  G16H50/30 ,  G16H50/20

Abstract: Methods and non-transitory machine-readable media associated with treatment plan identification are described. Treatment plan identification can include receiving first signaling configured to monitor user health data and receiving second signaling configured to monitor user behavior data. Treatment plan identification can include writing data that is based at least in part on a combination of the first signaling and the second signaling and identifying output data representative of a treatment plan for the user based at least in part on input data representative of the written data and additional user data. Output data representative of the treatment plan can be transmitted to a computing device accessible by the user, a computing device accessible by a provider, or both.

公开(公告)号：US20230043108A1

公开(公告)日：2023-02-09

申请号：US17396341

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Yuan He

IPC: H01L23/525 ,  H01L27/108

Abstract: Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate.