公开(公告)号：US20190066739A1

公开(公告)日：2019-02-28

申请号：US15692407

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC: G11C7/10 ,  G11C8/10

CPC classification number: G11C7/1006 ,  G11C8/10 ,  G11C29/023 ,  G11C29/028 ,  G11C2216/14 ,  G11C2216/22

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20180196705A1

公开(公告)日：2018-07-12

申请号：US15911490

申请日：2018-03-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, JR. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079

Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

公开(公告)号：US20250013364A1

公开(公告)日：2025-01-09

申请号：US18896573

申请日：2024-09-25

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F11/34 ,  G06F12/02 ,  G06F12/0888 ,  G06F12/0893

Abstract: Memory devices are disclosed. A memory device may include hybrid cache including single-level cell (SLC) blocks of memory and non-SLC blocks of memory. The memory device may further include a memory controller configured to disable, based on workload of the hybrid cache, a portion of the hybrid cache such that writes are only directed to another, different portion of the cache. Associated methods and systems are also disclosed.

公开(公告)号：US12131790B2

公开(公告)日：2024-10-29

申请号：US18125595

申请日：2023-03-23

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/34 ,  G06F12/02 ,  G06F12/0891 ,  G06F16/11 ,  G06F16/16 ,  G06F16/17 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3495 ,  G06F12/0891 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

公开(公告)号：US20240168879A1

公开(公告)日：2024-05-23

申请号：US18386760

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

公开(公告)号：US11914878B2

公开(公告)日：2024-02-27

申请号：US17576033

申请日：2022-01-14

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Antonio D. Bianco

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F2212/7211

Abstract: A method includes determining a health characteristic value of a block of memory cells, determining a difference between the health characteristic value and a health threshold, determining, based on the difference, a weight to associate with a block of memory cells, selecting, based on the weight, a block of memory cells for a media management operation; and performing a media management operation on the selected block of memory cells.

公开(公告)号：US11907536B2

公开(公告)日：2024-02-20

申请号：US18093069

申请日：2023-01-04

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0646 ,  G06F3/0679

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

公开(公告)号：US20230393736A1

公开(公告)日：2023-12-07

申请号：US17830166

申请日：2022-06-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Patrick R. Khayat ,  James Fitzpatrick ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  Ashutosh Malshe

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0679 ,  G06F3/0655

Abstract: One of a plurality of compaction strategies to be performed on the memory device based on at least one characteristic of a memory device is identified. Each of the plurality of compaction strategies is to program host data from at least one single-level cell (SLC) of the memory device to at least one quad-level cell (QLC) of the memory device. One or more host data from a host system is received. A compaction operation on the one or more host data using the one of the plurality of compaction strategies is performed.

公开(公告)号：US11829290B2

公开(公告)日：2023-11-28

申请号：US17247805

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Ashutosh Malshe ,  Peter Sean Feeley

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02

CPC classification number: G06F12/0253 ,  G06F2212/1044

Abstract: A processing device in a memory system determines a rate at which an amount of valid data is decreasing on a first block of the memory device and determines whether the rate at which the amount of valid data is decreasing on the first block satisfies a threshold criterion. Responsive to the rate at which the amount of valid data is decreasing on the first block satisfying the threshold criterion, the processing device performs a media management operation on the first block of the memory device.

公开(公告)号：US11810627B2

公开(公告)日：2023-11-07

申请号：US17886884

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Harish R. Singidi ,  Renato C. Padilla ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  Sampath K. Ratnam

IPC: G11C16/34 ,  G11C16/08 ,  G06F11/30 ,  G06F11/07

CPC classification number: G11C16/3431 ,  G06F11/076 ,  G06F11/3037 ,  G11C16/08 ,  G11C16/349 ,  G11C16/3427

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.