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    Adaptive write operations for a memory device
    101.
    发明授权
    Adaptive write operations for a memory device 有权

    公开(公告)号：US11942183B2

    公开(公告)日：2024-03-26

    申请号：US17502481

    申请日：2021-10-15

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

    IPC: G11C7/00 ,  G11C7/10

    CPC classification number: G11C7/1096 ,  G11C7/1051

    Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

    Memory cells for storing operational data
    107.
    发明授权
    Memory cells for storing operational data 有权

    公开(公告)号：US11783897B2

    公开(公告)日：2023-10-10

    申请号：US17875001

    申请日：2022-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

    IPC: G11C7/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

    Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

    Multi-component cell architectures for a memory device
    110.
    发明授权
    Multi-component cell architectures for a memory device 有权

    公开(公告)号：US11637145B2

    公开(公告)日：2023-04-25

    申请号：US17210571

    申请日：2021-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli

    IPC: G11C13/00 ,  G11C11/56 ,  G11C7/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

    Abstract: Methods, systems, and devices for multi-component cell architectures for a memory device are described. A memory device may include self-selecting memory cells that include multiple self-selecting memory components (e.g., multiple layers or other segments of a self-selecting memory material, separated by electrodes). The multiple self-selecting memory components may be configured to collectively store one logic state based on the polarity of a programming pulse applied to the memory cell. The multiple memory component layers may be collectively (concurrently) programmed and read. The multiple self-selecting memory components may increase the size of a read window of the memory cell when compared to a memory cell with a single self-selecting memory component. The read window for the memory cell may correspond to the sum of the read windows of each self-selecting memory component.

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