公开(公告)号：US20130343120A1

公开(公告)日：2013-12-26

申请号：US13974731

申请日：2013-08-23

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Carlo Lisi

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/009

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

公开(公告)号：US12288592B2

公开(公告)日：2025-04-29

申请号：US17873991

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

IPC: G11C29/50

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

公开(公告)号：US11929124B2

公开(公告)日：2024-03-12

申请号：US17597004

申请日：2020-11-11

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C29/52

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C29/52

Abstract: The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.

公开(公告)号：US11929121B2

公开(公告)日：2024-03-12

申请号：US17690573

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/26 ,  G11C16/30

Abstract: Apparatuses, methods, and systems for storing one data value by programming a first memory cell and a second memory cell are disclosed. The first memory cell and the second memory cell may each be programmed to a first data state, a second data state, or a third data state, and the one data value can correspond to a combination of the first data state, the second data state, or the third data state to which the first memory cell and the second memory cell are programmed, where two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.

公开(公告)号：US11887689B2

公开(公告)日：2024-01-30

申请号：US17585307

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

CPC classification number: G11C7/12 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2273 ,  G11C11/2293

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US11804271B2

公开(公告)日：2023-10-31

申请号：US17726351

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo ,  Daniele Balluchi

IPC: G11C11/00 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C16/30 ,  G11C16/0483

Abstract: Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.

公开(公告)号：US11798608B2

公开(公告)日：2023-10-24

申请号：US17646259

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Michele Maria Venturini

IPC: G11C11/22 ,  G11C7/12 ,  H10B53/20

CPC classification number: G11C11/2273 ,  G11C7/12 ,  G11C11/221 ,  H10B53/20

Abstract: Methods, systems, and devices for techniques to perform a sense operation are described. In some examples, a memory device may include a pair of transistor to precharge a digit line. A first transistor of the pair of transistors may be coupled with a first node and a second transistor of the pair of transistors may be coupled with a second node. In some cases, the first node and the second node may be selectively coupled via a transistor. The first and second transistors may be activated to precharge the first and second nodes. In some examples, a pulse may be applied to a capacitor coupled with the second node to transfer a charge to the digit line. In some cases, the cascode transistor may maintain or control the voltage of the digit line to be at or below an upper operating voltage of the memory cell.

公开(公告)号：US11756602B2

公开(公告)日：2023-09-12

申请号：US17646261

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Michele Maria Venturini

IPC: G11C11/22 ,  G11C16/28 ,  G11C16/04

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C16/0483 ,  G11C16/28

Abstract: Methods, systems, and devices for sensing component with a common node are described. A set of sense circuits of a memory device may include a shared differential amplifier having a first branch for each sense circuit and a shared second branch, as well as a shared common node. A respective latch of each sense amplifier may be initialized to a second logic state, and the common node may undergo a voltage ramp to determine the state stored in the memory cell. If the memory cell stores the first logic state, the sense amplifier may couple with the common node to draw the current and switch the state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state the current may not be drawn and the state of the latch may not switch.

公开(公告)号：US11749360B2

公开(公告)日：2023-09-05

申请号：US17573229

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: Methods, systems, and devices that support techniques for programming self-selecting memory are described. Received data may include a first group of bits that each have a first logic value and a second group of bits that each have a second logic value. The first and second group of bits may be stored in a first set of memory cells and a second set of memory cells, respectively. A first programming operation for writing the second logic value to both the first and second set of memory cells and verifying whether the second logic value is written to each of the first set of memory cells, the second set of memory cells, or both may be performed. A second programming operation may write the first logic value to either the first set of memory cells or the second set of memory cells based on a result of the verification.

公开(公告)号：US11735244B2

公开(公告)日：2023-08-22

申请号：US17562557

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/00 ,  G11C11/56

CPC classification number: G11C11/2273 ,  G11C11/005 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293 ,  G11C11/5657 ,  G11C11/22

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.