公开(公告)号：US5767409A

公开(公告)日：1998-06-16

申请号：US753683

申请日：1996-11-27

申请人： Seiji Yamaguchi

发明人： Seiji Yamaguchi

IPC分类号： G01N15/06 ,  G01N22/00 ,  G01N22/04 ,  G01S7/288 ,  G01S13/36 ,  G01S15/36 ,  G01S17/36 ,  G01S3/82 ,  G01N29/02

CPC分类号： G01S17/36 ,  G01N22/00 ,  G01N22/04 ,  G01S13/36 ,  G01S7/288 ,  G01N2291/048 ,  G01S15/36

摘要： A phase difference measuring apparatus obtains a first receive signal by transmitting and receiving a to-be-measured material in a reference state and a second receive signal by transmitting and receiving a signal wave to and from that material in a measured state. The apparatus finds a reference phase difference .theta..sub.1 from the transmit wave and first receive signal and an apparent phase difference .theta..sub.2 ' from the transmit wave and second receive signal. The apparatus adds the apparent phase difference .theta..sub.2 ' to a product of the number of rotations, n, the apparent phase difference .theta..sub.2 ' passes through a given reference point and an angle of 360.degree. to find a true phase difference .theta..sub.2. The apparatus varies the number of rotations, n, to n+1 when the apparent phase difference .theta..sub.2 ', while being increased, passes through the reference point and that number of rotations, n, to n=n-1 when the apparent phase difference .theta..sub.2 ', while being decreased, passes through the reference point.

摘要翻译： 相位差测量装置通过在测量状态下发送和接收来自该材料的信号波，通过在参考状态和第二接收信号中发送和接收被测量材料来获得第一接收信号。 该装置从发射波和第一接收信号找到参考相位差θ1，并从发射波和第二接收信号中发现表观相位差θ2'。 该装置将视在相位差θ2'添加到旋转次数n的乘积，n，通过给定参考点的视差相位差θ2'和360°的角度以找到真相相位差θ2。 当表观相位差θ2'同时增加时，通过参考点将旋转次数n改变为n + 1，并且当视在相位差 θ2'，同时减小，通过参考点。

公开(公告)号：US5463751A

公开(公告)日：1995-10-31

申请号：US358688

申请日：1994-12-19

申请人： Hirokazu Yonezawa ,  Seiji Yamaguchi

发明人： Hirokazu Yonezawa ,  Seiji Yamaguchi

IPC分类号： G06F12/10

CPC分类号： G06F12/1027

摘要： A semiconductor memory device has an address translator and a comparator. An entry of the address translator includes an associative memory cell array for storing and comparing a logical address of at least m bits. A first decoder generates a first word signal for the associative memory cell array. A first random access memory cell array stores a physical address of m bits. A controller generates a word signal for the first random access memory cell according to the first word signal and a result of a comparison by the associative memory cell array. A second random access memory cell stores a physical address of m bits. The second random access memory cell is physically disposed near the first random access memory cell array. A second decoder generates a second word signal for the second random access memory cell array. Outputs of the first and second random access memory cell arrays are connected to and compared by the comparator which outputs a signal upon coincidence between the outputs of the first and second random access memory cell arrays.

摘要翻译： 半导体存储器件具有地址转换器和比较器。 地址转换器的条目包括用于存储和比较至少m位的逻辑地址的关联存储单元阵列。 第一解码器产生关联存储单元阵列的第一字信号。 第一随机存取存储单元阵列存储m位的物理地址。 控制器根据第一字信号产生用于第一随机存取存储器单元的字信号和由关联存储单元阵列的比较结果。 第二随机存取存储器单元存储m位的物理地址。 第二随机存取存储器单元物理地布置在第一随机存取存储单元阵列附近。 第二解码器产生用于第二随机存取存储单元阵列的第二字信号。 第一和第二随机存取存储单元阵列的输出连接到比较器，比较器在第一和第二随机存取存储单元阵列的输出之间一致地输出信号。

公开(公告)号：US5446851A

公开(公告)日：1995-08-29

申请号：US257454

申请日：1994-06-08

申请人： Seiji Yamaguchi

发明人： Seiji Yamaguchi

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/445 ,  G06F11/00

CPC分类号： G06F9/30145 ,  G06F11/004 ,  G06F8/66 ,  G06F9/3017 ,  G06F9/328 ,  G06F9/3853 ,  G06F9/3861

摘要： An instruction supplier for a microprocessor prevents a functional error operation of the microprocessor. In the instruction supplier, an instruction register temporarily stores an inputted instruction therein, and an instruction memory stores at least one instruction therein. At least one comparator is provided for detecting whether or not at least one instruction stored in the instruction memory agrees with the instruction stored in the instruction register, respectively, by comparing them, and for outputting a comparison result signal for indicating the comparison result. Furthermore, an instruction generator generates at least one specific instruction in accordance with the comparison signal, and then, an instruction selector selects either one of the instruction stored in the instruction register and the specific instruction generated by the instruction generator to be executed, and outputs the selected instruction.

摘要翻译： 微处理器的指令提供器防止微处理器的功能错误操作。 在指令供给器中，指令寄存器临时存储输入的指令，指令存储器存储至少一个指令。 提供至少一个比较器，用于通过比较它们来检测存储在指令存储器中的至少一个指令是否与存储在指令寄存器中的指令一致，并且用于输出用于指示比较结果的比较结果信号。 此外，指令生成器根据比较信号生成至少一个特定指令，然后指令选择器选择存储在指令寄存器中的指令中的任何一个以及要执行的指令发生器产生的特定指令，并且输出 所选指令。

公开(公告)号：US5434989A

公开(公告)日：1995-07-18

申请号：US323528

申请日：1994-10-11

申请人： Seiji Yamaguchi

发明人： Seiji Yamaguchi

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F9/3804 ,  G06F12/0831 ,  G06F12/0875 ,  G06F9/3824

摘要： A cache memory device including first and second address selectors and a control device for controlling the selection of two addresses out of four types of addresses. The four address types are instructions addresses successively generated by an increment of a program counter, a branch address for instruction fetch in a branch target based on a conditional branch instruction or the like, a data address for data access based on load instruction or store instruction, and a physical address for regulating data consistency between the cache memory device and other memory devices. A first memory array for storing tag addresses and a second memory array for storing instructions and data have two ports to access two selected addresses received from the first and second address selectors independently. Accordingly, access penalties by an RISC microprocessor are reduced in a processor unit in a multiprocessor system.

摘要翻译： 一种包括第一和第二地址选择器的高速缓冲存储器设备和用于控制四种地址中的两个地址的选择的控制设备。 四种地址类型是由程序计数器的增量连续产生的指令地址，基于条件转移指令等的转移目标中指令取出的分支地址，基于加载指令或存储指令的数据访问数据地址 以及用于调节高速缓冲存储器件和其它存储器件之间的数据一致性的物理地址。 用于存储标签地址的第一存储器阵列和用于存储指令和数据的第二存储器阵列具有两个端口以独立地访问从第一和第二地址选择器接收的两个选定的地址。 因此，RISC微处理器的访问惩罚在多处理器系统中的处理器单元中减少。

公开(公告)号：US5252863A

公开(公告)日：1993-10-12

申请号：US848372

申请日：1992-03-09

申请人： Tsuguyasu Hatsuda ,  Seiji Yamaguchi

发明人： Tsuguyasu Hatsuda ,  Seiji Yamaguchi

IPC分类号： G11C11/418 ,  G11C8/08 ,  G11C11/407 ,  H03K19/017 ,  H03K19/20

CPC分类号： H03K19/01728 ,  G11C8/08

摘要： A drive circuit provided in a semiconductor integrated circuit can perform a high-speed switching in compliance with a synchronizing signal and has a number of drive circuit elements. Each of the drive circuit elements is provided with a P-channel MOSFET, an N-channel MOSFET, and an inverter circuit to generate an output signal. The P-channel MOSFET has a gate connected to an input line of a first input signal and a source connected to a source line whereas the N-channel MOSFET has a gate connected to the input line of the first input signal, a source connected to an input line of an inverted logic signal of a second input signal, and a drain connected to a drain of the P-channel MOSFET. The inverter circuit has a gate connected to the drain of the P-channel MOSFET to generate the output signal in synchronization with the second input signal.

摘要翻译： 设置在半导体集成电路中的驱动电路可以根据同步信号执行高速切换，并且具有多个驱动电路元件。 每个驱动电路元件设置有P沟道MOSFET，N沟道MOSFET和逆变器电路以产生输出信号。 P沟道MOSFET具有连接到第一输入信号的输入线和连接到源极线的源极的栅极，而N沟道MOSFET具有连接到第一输入信号的输入线的栅极，源极连接到 第二输入信号的反相逻辑信号的输入线和连接到P沟道MOSFET的漏极的漏极。 逆变器电路具有连接到P沟道MOSFET的漏极的栅极，以与第二输入信号同步地产生输出信号。

公开(公告)号：US5054002A

公开(公告)日：1991-10-01

申请号：US331784

申请日：1989-04-03

申请人： Kazuki Ninomiya ,  Seiji Yamaguchi

发明人： Kazuki Ninomiya ,  Seiji Yamaguchi

IPC分类号： G11C11/41 ,  G06F7/00 ,  G11C8/18 ,  G11C11/413

CPC分类号： G11C8/18

摘要： A memory unit includes an array of memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A decoder receives an address signal at a timing which follows an occurrence of a clock signal by a given time t1. The address signal is in synchronism with the clock signal. The clock signal has a preset period t0. The decoder decodes the address signal into a word signal and outputs the word signal at a timing which follows the reception of the address signal by a given time t2. A delay device delays the clock signal by a preset time "t" and thereby converts the clock signal into a control signal. An access to a word of the memory cells is performed via one of the word lines in accordance with the word signal at a timing determined by the control signal. The bit lines are precharged at a timing determined by the control signal. The preset time "t" is longer than a sum of the time t1 and t2 but shorter than a half of the period t0.

摘要翻译： 存储单元包括存储单元阵列。 字线连接到存储单元。 位线连接到存储单元。 解码器在给定时间t1之后的时钟信号发生的定时接收地址信号。 地址信号与时钟信号同步。 时钟信号具有预设时段t0。 解码器将地址信号解码为字信号，并在接收到地址信号的定时将字信号输出给定时间t2。 延迟装置将时钟信号延迟预设时间“t”，从而将时钟信号转换成控制信号。 在由控制信号确定的定时根据字信号经由一条字线执行对存储器单元的字的访问。 位线在由控制信号确定的定时被预充电。 预设时间“t”比时间t1和t2之和长但小于周期t0的一半。

公开(公告)号：US4942640A

公开(公告)日：1990-07-24

申请号：US283324

申请日：1988-12-01

申请人： Nobuhiro Hayashi ,  Toshiichiro Tanaka ,  Seiji Yamaguchi ,  Hidetoshi Imai

发明人： Nobuhiro Hayashi ,  Toshiichiro Tanaka ,  Seiji Yamaguchi ,  Hidetoshi Imai

IPC分类号： A47L9/19 ,  A47L9/28 ,  H02P23/00 ,  H02P25/04

CPC分类号： A47L9/2894 ,  A47L9/2815 ,  A47L9/2842 ,  A47L9/2857 ,  Y02B40/82

摘要： An electric vacuum cleaner is disclosed, wherein input power for a motor blower contained in the body of the same can be controlled by switches (6), (7) provided to the handle of a hose. Input power for motor blower is automatically controlled in accordance with the amount of dust passing through suction air path. A switch (22) is provided which is capable of changing suction force temporarily in automatic operation mode by operation of the user, irrespective of the amount of dust.

摘要翻译： PCT No.PCT / JP88 / 00337 Sec。 371日期：1988年12月1日 102（e）日期1988年12月1日PCT提交1988年4月1日PCT公布。 公开号WO88 / 07347 日本特开昭通1988年10月6日公开了一种电动吸尘器，其中包含在其主体内的电动机鼓风机的输入功率可以由提供给软管手柄的开关（6），（7）控制。 电机鼓风机输入功率根据吸入风道的灰尘量自动控制。 提供了一种开关（22），其能够通过使用者的操作在自动运行模式下临时地改变吸力，而与灰尘的量无关。

公开(公告)号：US09653661B2

公开(公告)日：2017-05-16

申请号：US12926253

申请日：2010-11-04

申请人： Yoshinobu Suehiro ,  Seiji Yamaguchi ,  Katsunori Arakane ,  Koji Tasumi

发明人： Yoshinobu Suehiro ,  Seiji Yamaguchi ,  Katsunori Arakane ,  Koji Tasumi

IPC分类号： H01L21/603 ,  H01L33/56 ,  H01L33/54 ,  H01L23/00 ,  H01L25/075 ,  H01L33/48

CPC分类号： H01L33/56 ,  H01L24/97 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/54 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2933/005 ,  H01L2924/00

摘要： A method of manufacturing a light-emitting device includes a hole forming process for forming a through-hole that continues from a front surface to a back surface of a mounting substrate, a pattern forming process for continuously forming a circuit pattern on an inner surface of the through-hole in the mounting substrate, from an end portion of the through-hole on the front surface of the mounting substrate to a mounting portion of a light-emitting element, and on a periphery of the through-hole on the back surface of the mounting substrate, a mounting process for mounting the light-emitting element on the mounting portion, and a hot pressing process in that an inorganic material softened by heating is placed on the surface of the mounting substrate and is advanced into the through-hole while sealing the light-emitting element by pressing and bonding the inorganic material to the surface of the mounting substrate.

公开(公告)号：US08860057B2

公开(公告)日：2014-10-14

申请号：US13550529

申请日：2012-07-16

申请人： Seiji Yamaguchi ,  Koji Tasumi

发明人： Seiji Yamaguchi ,  Koji Tasumi

IPC分类号： H01L33/00 ,  H01L33/50 ,  H01L33/54 ,  C03B19/06 ,  H01L25/075 ,  H01L33/56

CPC分类号： H01L25/0753 ,  C03B19/063 ,  H01L33/50 ,  H01L33/54 ,  H01L33/56 ,  H01L2224/16225 ,  Y02P40/57

摘要： The light emitting device 10 comprises a mounting substrate 11, LED chips 20 flip-chip bonded on the mounting substrate 11, and a glass sealing member 30 made of a plate-shaped glass material that seals the LED chips 20 formed on the mounting substrate 11. Here, the glass sealing member 30 is in a state in which fine voids are almost evenly dispersed and distributed between the powder grains of the glass material, and the powder grains are connected with each other, and the fine bumps/dips 30a are almost evenly dispersed and distributed on the surface of the glass sealing member 30.

摘要翻译： 发光装置10包括安装基板11，贴合在安装基板11上的LED芯片20以及由形成在安装基板11上的LED芯片20的板状玻璃材料制成的玻璃密封部件30 这里，玻璃密封构件30处于微小的空隙几乎均匀地分散并分布在玻璃材料的粉末颗粒之间并且粉末颗粒彼此连接的状态，并且微小的凸起/凹陷30a几乎 均匀分散并分布在玻璃密封件30的表面上。

公开(公告)号：US20110250187A1

公开(公告)日：2011-10-13

申请号：US13071445

申请日：2011-03-24

申请人： Shunji Tomatsu ,  William Sly ,  Jeffrey Grubb ,  Tatsuo Nishioka ,  Ken-ichi Miyamoto ,  Seiji Yamaguchi

发明人： Shunji Tomatsu ,  William Sly ,  Jeffrey Grubb ,  Tatsuo Nishioka ,  Ken-ichi Miyamoto ,  Seiji Yamaguchi

IPC分类号： A61K35/54 ,  A61P3/00 ,  A61K48/00 ,  C12N9/16 ,  A61K38/46

CPC分类号： A61K38/465 ,  C12Y301/03001

摘要： The present invention provides compositions and methods for use in enzyme replacement therapy. The inventors disclose a method of producing membrane bound enzymes in an active soluble form by eliminating the glycosylphosphatidylinositol (GPI) membrane anchor. In particular the inventors disclose a soluble active form of the membrane bound enzyme TNSALP which they produced by deleting the GPI anchor single peptide sequence. They have further shown that this composition is useful for treatment of hypophosphatasia. The inventors also disclose oligo acid amino acid variants thereof which specifically target bone tissue.

摘要翻译： 本发明提供了用于酶替代疗法的组合物和方法。 本发明人公开了通过消除糖基磷脂酰肌醇（GPI）膜锚定点来生产活性可溶形式的膜结合酶的方法。 特别地，本发明人公开了通过缺失GPI锚单肽序列产生的膜结合酶TNSALP的可溶性活性形式。 他们进一步表明，该组合物可用于治疗下尿失禁。 本发明人还公开了特异性靶向骨组织的寡糖氨基酸变体。