公开(公告)号：US20190148507A1

公开(公告)日：2019-05-16

申请号：US15989606

申请日：2018-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L29/423 ,  H01L29/10 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure, in some embodiments, relates to a transistor device within an active area having a shape configured to reduce a susceptibility of the transistor device to performance degradation (e.g., the kink effect) caused by divots in an adjacent isolation structure. The transistor device has a substrate including interior surfaces defining a trench within an upper surface of the substrate. One or more dielectric materials are arranged within the trench. The one or more dielectric materials define an opening exposing the upper surface of the substrate. The opening has a source opening over a source region within the substrate, a drain opening over a drain region within the substrate, and a channel opening between the source opening and the drain opening. The source opening and the drain opening have widths smaller than the channel opening. A gate structure extends over the opening between the source and drain regions.

公开(公告)号：US10283512B2

公开(公告)日：2019-05-07

申请号：US15584314

申请日：2017-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L27/11531 ,  H01L27/11517 ,  H01L27/11526 ,  H01L29/66 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11551 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11536 ,  H01L27/11539

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US20190097009A1

公开(公告)日：2019-03-28

申请号：US16166603

申请日：2018-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/792 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/11521

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.

公开(公告)号：US10163919B2

公开(公告)日：2018-12-25

申请号：US14980147

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu

IPC: H01L21/28 ,  H01L27/11 ,  H01L29/66 ,  H01L21/306 ,  H01L21/321 ,  H01L27/105 ,  H01L21/8234 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11563 ,  H01L27/11568

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

公开(公告)号：US09911805B2

公开(公告)日：2018-03-06

申请号：US15349100

申请日：2016-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

公开(公告)号：US09831262B2

公开(公告)日：2017-11-28

申请号：US14984095

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Tzu-Yu Chen

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a select transistor and a control transistor laterally spaced apart over a substrate. A select gate electrode and a control gate electrode are disposed over a high-k gate dielectric layer and a memory gate oxide. A logic region is disposed adjacent to the memory region and has a logic device including a metal gate electrode disposed over the high-k gate dielectric layer and a logic gate oxide. The select gate electrode and the control gate electrode can be polysilicon electrodes.

公开(公告)号：US09735245B2

公开(公告)日：2017-08-15

申请号：US14481987

申请日：2014-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ya-Chen Kao

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/78

CPC classification number: H01L29/42344 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

公开(公告)号：US20170170189A1

公开(公告)日：2017-06-15

申请号：US14967813

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L27/115 ,  H01L29/49 ,  H01L21/321 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/32115 ,  H01L21/32139 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region having a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer and an embedded memory region disposed adjacent to the logic region. The embedded memory region has a split gate flash memory cell including a select gate and a control gate. The control gate or the select gate is a metal gate separated from the substrate by a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

公开(公告)号：US20170170188A1

公开(公告)日：2017-06-15

申请号：US14967767

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/28 ,  H01L29/45 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66833

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a logic region and an embedded memory region disposed adjacent to the logic region. The logic region has a logic device disposed over a substrate and including a first metal gate disposed over a first high-k gate dielectric layer. The memory region has a non-volatile memory (NVM) device including a second metal gate disposed over a second high-k gate dielectric layer. By having HKMG structures in both the logic region and the memory region, IC performance is improved and further scaling becomes possible in emerging technology nodes.

公开(公告)号：US20170133388A1

公开(公告)日：2017-05-11

申请号：US14933046

申请日：2015-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.