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公开(公告)号：US11916546B2
公开(公告)日：2024-02-27
申请号：US17185564
申请日：2021-02-25
发明人： Semen Syroiezhin , Ivan Jevtic , Valentyn Solomko
IPC分类号： H03K17/74 , H03K17/14 , H03K17/16 , H03K17/041 , H04B1/44
CPC分类号： H03K17/16 , H03K17/04106 , H03K17/74 , H03K17/145 , H03K2217/0054 , H03K2217/0081 , H04B1/44
摘要： A radio frequency switch device includes a first transistor and a second transistor; a compensation network coupled between a body terminal of the first transistor and a source/drain terminal of the second transistor; and a bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to the body terminal of the first transistor, wherein the bootstrapping network establishes a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the bootstrapping network establishes a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal.
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公开(公告)号：US11916059B2
公开(公告)日：2024-02-27
申请号：US17411060
申请日：2021-08-25
发明人： Andre Schmenn , Stefan Pompl , Damian Sojka , Katharina Umminger
IPC分类号： H01L23/60 , H01L27/02 , H01L21/78 , H01L23/538 , H01L23/00 , H01L25/07 , H01L25/00 , H01L29/74 , H02H9/04 , H01L27/07
CPC分类号： H01L27/0248 , H01L21/78 , H01L23/5386 , H01L23/5389 , H01L23/60 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/072 , H01L25/50 , H01L27/0255 , H01L27/0262 , H01L27/0292 , H01L29/7416 , H02H9/04 , H01L27/0744 , H01L29/74 , H01L2224/214 , H01L2224/95001 , H01L2924/1203 , H01L2924/1301 , H01L2924/30205 , H01L2924/1301 , H01L2924/00012 , H01L2924/1203 , H01L2924/00012
摘要： An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.
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113.发明授权公开(公告)号：US11915999B2
公开(公告)日：2024-02-27
申请号：US18103865
申请日：2023-01-31
发明人： Tomasz Naeve , Ralf Otremba , Thorsten Scharf , Markus Dinkel , Martin Gruber , Elvir Kahrimanovic
IPC分类号： H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/40 , H01L25/065 , H01L25/075 , H01L25/04 , H02P27/06
CPC分类号： H01L23/49568 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/4012 , H01L23/49503 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L25/043 , H01L25/0655 , H01L25/0756 , H01L2924/181 , H02P27/06 , H02P2201/03
摘要： A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.
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公开(公告)号：US20240063843A1
公开(公告)日：2024-02-22
申请号：US18450147
申请日：2023-08-15
IPC分类号： H04B1/58 , H04B1/3888
CPC分类号： H04B1/587 , H04B1/586 , H04B1/3888
摘要： A transceiver hybrid includes a multi-layer laminated hybrid comprising a coupler, the coupler including a first metal layer in a first layer of the multi-layer laminated hybrid having a first end coupled to a termination terminal and a second end coupled to a quadrature terminal; and a second metal layer in a second layer of the multi-layer laminated hybrid having a first end coupled to an antenna terminal, and a second end coupled to an in-phase terminal, wherein a width of the first metal layer is greater than a width of the second metal layer, such that a registration error margin is formed between the first metal layer and the second metal layer.
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公开(公告)号：US20240063812A1
公开(公告)日：2024-02-22
申请号：US17820975
申请日：2022-08-19
IPC分类号： H03M3/00
摘要： In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.
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公开(公告)号：US20240061074A1
公开(公告)日：2024-02-22
申请号：US18452025
申请日：2023-08-18
摘要： An apparatus includes interface circuitry configured to receive data indicating a measurement signal of a radar sensor. The apparatus further includes processing circuitry configured to determine a rate at which the measurement signal crosses a predefined value based on the data and determine presence of at least one of an interference signal and a target motion in a field of view of the radar sensor based on the rate.
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公开(公告)号：US11906996B2
公开(公告)日：2024-02-20
申请号：US17348252
申请日：2021-06-15
发明人： Stefano Bonomi
摘要： In accordance with an embodiment, a circuit includes: a pass transistor drive circuit including an digital input, and at least one output configured to be coupled to at least one pass transistor; a digital feedback circuit having a first analog input configured to be coupled to the at least one pass transistor, and a digital output coupled to the digital input of the pass transistor drive circuit; and an analog feedback circuit including a second analog input configured to be coupled to the at least one pass transistor, and an analog output coupled to an over voltage node of the pass transistor drive circuit, where the analog feedback circuit has a DC gain greater than zero.
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公开(公告)号：US11901883B2
公开(公告)日：2024-02-13
申请号：US17456857
申请日：2021-11-29
IPC分类号： H03K17/0812 , H03K17/18
CPC分类号： H03K17/08122 , H03K17/18 , H03K2217/0027
摘要： Overload detection and protection for power switch circuits. For circuits with faster switching speed, fast fault detection and response to a detected overload condition may be desirable. Detection circuitry may monitor a voltage on the control terminal of one or more power switches. Based on empirical measurements, in an overload condition of a power switch circuit, e.g., a half-bridge circuit, the voltage at the control terminal may increase, and in some examples, increase to a magnitude that is greater than a supply voltage. A comparator may detect a voltage increase that exceeds a voltage magnitude threshold, output an indication to control circuitry for the power switch circuit, and the control circuitry may take action to protect the rest of the circuitry, such as reduce voltage or shut off the power switch circuit.
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公开(公告)号：US11901675B2
公开(公告)日：2024-02-13
申请号：US17825054
申请日：2022-05-26
CPC分类号： H01R13/6683 , G01R15/202 , G01R15/205 , G01R15/207
摘要： A power connector is provided that is configured to conduct a current and includes a conductive frame including a base structure, an extension structure, and a cap structure that define a current path for the current. The base structure is configured to be coupled to a current supply for receiving the current therefrom. The cap structure is configured to be coupled to an electrical interface of a device to be supplied with the current and outputs the current from the connector to the electrical interface of the device. The extension structure is coupled to and vertically extends between the base structure and the cap structure. The extension structure includes a current constriction region that is configured to cause a defined magnetic field of the current flowing through the current constriction region at a predefined position.
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公开(公告)号：US11899826B2
公开(公告)日：2024-02-13
申请号：US17547906
申请日：2021-12-10
发明人： Christoph Lampe , Martin Steinbach
IPC分类号： G06F21/72
CPC分类号： G06F21/72
摘要： According to an embodiment, a security controller is described comprising a memory storing data elements of a data array and a processing circuit configured to determine a power of two such that number of data elements is higher than the power of two but at most equal to double the power of two, determine random first and second integers, change indices of a predefined sequence of indices, comprising performing a first change of the index according to a first permutation if it is lower than the power of two, performing a second change of the index by adding a third integer modulo data array length and performing a third change of the index by a second permutation if it is, following the second change, lower than the power of two, and process the data elements in an order of the changed indices.
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