公开(公告)号：US07227482B2

公开(公告)日：2007-06-05

申请号：US11408941

申请日：2006-04-24

申请人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

发明人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Akira Hayakawa ,  Hiroyuki Hagiwara ,  Yoshitaka Jingu ,  Kazuyuki Kobayashi ,  Toshiro Tsukada

IPC分类号： H03M3/00

CPC分类号： H03M3/34 ,  H03M3/40 ,  H03M3/402 ,  H03M3/424 ,  H03M3/454

摘要： In a first-order complex band-pass filter, multiplexers are alternately switched over between time intervals of phases A and B, where the multiplexers includes two multiplexers provided at input and output stages, and a multiplexer provided in a feedback circuit of each of first-order filters and being switching over whether to invert a sign of a feedback signal. Then in a circuit part sandwiched between the multiplexers, a processing performed by an I circuit part and a processing performed by a Q circuit part are alternately switched over so that a sign of a signal inputted to an adder is inverted.

摘要翻译： 在一阶复数带通滤波器中，多路复用器在相位A和B的时间间隔之间交替切换，其中多路复用器包括在输入和输出级提供的两个多路复用器，以及多路复用器，其设置在第一 - 顺序滤波器并切换是否反转反馈信号的符号。 然后在夹在多路复用器之间的电路部分中，交替地切换由I电路部分执行的处理和由Q电路部分执行的处理，使得输入到加法器的信号的符号反转。

公开(公告)号：US07178008B2

公开(公告)日：2007-02-13

申请号：US10370172

申请日：2003-02-18

申请人： Tetsuo Hironaka ,  Mattausch Hans Juergen ,  Takeshi Hiramatsu

发明人： Tetsuo Hironaka ,  Mattausch Hans Juergen ,  Takeshi Hiramatsu

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3012 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3885

摘要： A parallel processor has a plurality of operation units that execute operation instructions, and a multi-bank register file in which a plurality of banks each having a plurality of registers are formed. Each of machine instructions, which are input simultaneously, is split into a plurality of nano-instructions each of which includes at least one of an access instruction and operation instruction. The output clock cycles of operation instructions with respect to the operation units are arbitrated. Furthermore, the output clock cycles of access instructions to the multi-bank register file are arbitrated so as to prevent access instructions from contending in an identical bank in the multi-bank register file.

摘要翻译： 并行处理器具有执行操作指令的多个操作单元，以及多存储体寄存器堆，其中形成多个具有多个寄存器的存储体。 每个同时输入的机器指令被分割成多个纳入指令，每个指令包括访问指令和操作指令中的至少一个。 对操作单元的操作指令的输出时钟周期进行仲裁。 此外，对多存储体寄存器堆的访问指令的输出时钟周期进行仲裁，以防止访问指令在多存储体寄存器堆中的相同存储体中竞争。

公开(公告)号：US20060194559A1

公开(公告)日：2006-08-31

申请号：US11354231

申请日：2006-02-15

申请人： Akira Hyogo ,  Satoshi Tanaka ,  Tetsuro Sawai ,  Kenichi Agawa ,  Hirotada Honma ,  Ryutaro Saito ,  Tomoki Hikichi ,  Keitaro Sekine

发明人： Akira Hyogo ,  Satoshi Tanaka ,  Tetsuro Sawai ,  Kenichi Agawa ,  Hirotada Honma ,  Ryutaro Saito ,  Tomoki Hikichi ,  Keitaro Sekine

IPC分类号： H04B1/26

CPC分类号： H04B1/26 ,  H03D7/165

摘要： A radio-frequency circuit comprises a low-noise amplifier, an NMOS mixer for converting a radio-frequency signal output from the low-noise amplifier into an intermediate-frequency signal, a polyphase filter for removing image noises, and a PMOS mixer for converting the intermediate-frequency signal passed through the polyphase filter into a baseband signal.

摘要翻译： 射频电路包括低噪声放大器，用于将从低噪声放大器输出的射频信号转换为中频信号的NMOS混频器，用于去除图像噪声的多相滤波器，以及用于转换的PMOS混合器 中频信号通过多相滤波器进入基带信号。

公开(公告)号：US07098437B2

公开(公告)日：2006-08-29

申请号：US10200332

申请日：2002-07-23

申请人： Masatoshi Ishikawa ,  Idaku Ishii ,  Takashi Komuro ,  Shingo Kagami

发明人： Masatoshi Ishikawa ,  Idaku Ishii ,  Takashi Komuro ,  Shingo Kagami

IPC分类号： G01J1/42

CPC分类号： G01J1/4228 ,  G01J1/0204 ,  H04N5/335

摘要： A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is provided at an output of each of the processing elements. The selecting circuit selects an input source from a group consisting of upper, lower, left, and right processing elements and a zero signal.

公开(公告)号：US07088084B2

公开(公告)日：2006-08-08

申请号：US11205491

申请日：2005-08-16

申请人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Kohei Onizuka

发明人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Kohei Onizuka

IPC分类号： G05F1/40

CPC分类号： H02M3/158 ,  H02M3/156

摘要： A voltage control circuit is connected to a voltage source. The voltage control circuit changes voltages of n different values and outputs them to an output node of the voltage control circuit according to control signals. A first switch element is connected between the output node of the voltage control circuit and a reference voltage node, and a second switch element is connected between the output node of the voltage control circuit and an output node of the voltage source. The first switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a first voltage to a second voltage that is lower than the first voltage, and the second switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a second voltage to a first voltage.

公开(公告)号：US20060057845A1

公开(公告)日：2006-03-16

申请号：US11207562

申请日：2005-08-19

申请人： Mitsumasa Koyanagi ,  Hiroyuki Kurino ,  Toshiaki Kurino ,  Jeoung Shim

发明人： Mitsumasa Koyanagi ,  Hiroyuki Kurino ,  Toshiaki Kurino ,  Jeoung Shim

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/78

摘要： There is disclosed a method of forming a nickel film on a silicon substrate or a silicon film, followed by applying an annealing process such that a final annealing temperature TH is in the range of 500° C.

摘要翻译： 公开了在硅衬底或硅膜上形成镍膜的方法，然后进行退火处理，使得最终退火温度TH在500℃的范围内。

公开(公告)号：US20060038544A1

公开(公告)日：2006-02-23

申请号：US11205491

申请日：2005-08-16

申请人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Kohei Onizuka

发明人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Kohei Onizuka

IPC分类号： G05F1/40

CPC分类号： H02M3/158 ,  H02M3/156

摘要： A voltage control circuit is connected to a voltage source. The voltage control circuit changes voltages of n different values and outputs them to an output node of the voltage control circuit according to control signals. A first switch element is connected between the output node of the voltage control circuit and a reference voltage node, and a second switch element is connected between the output node of the voltage control circuit and an output node of the voltage source. The first switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a first voltage to a second voltage that is lower than the first voltage, and the second switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a second voltage to a first voltage.

摘要翻译： 电压控制电路连接到电压源。 电压控制电路根据控制信号改变n个不同值的电压并将其输出到电压控制电路的输出节点。 第一开关元件连接在电压控制电路的输出节点和参考电压节点之间，第二开关元件连接在电压控制电路的输出节点和电压源的输出节点之间。 第一开关元件被控制为当电压控制电路将输出节点的电压从第一电压改变为低于第一电压的第二电压时导通，并且第二开关元件被控制为 当电压控制电路将输出节点的电压从第二电压改变为第一电压时导通。

公开(公告)号：US06962882B2

公开(公告)日：2005-11-08

申请号：US10170325

申请日：2002-06-12

申请人： Shinji Nozaki ,  Kazuo Uchida ,  Hiroshi Morisaki

发明人： Shinji Nozaki ,  Kazuo Uchida ,  Hiroshi Morisaki

IPC分类号： H01L21/316 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/469 ,  H01L21/768

CPC分类号： H01L21/02164 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/31695 ,  H01L21/32055 ,  H01L21/7682 ,  H01L2221/1047

摘要： While a crucible containing an Si material and a substrate to be processed are set in a chamber, Ar gas is supplied into the chamber and the Si material is evaporated by heating, thereby forming a nanoparticle thin film of Si on the substrate. This substrate is then annealed in an oxygen atmosphere to oxidize Si, forming a nanoparticle oxide thin film consisting of SiO2.

摘要翻译： 当将含有Si材料和待处理基板的坩埚放置在室中时，将Ar气供给到室中，通过加热蒸发Si材料，从而在衬底上形成Si纳米颗粒薄膜。 然后将该衬底在氧气氛中退火以氧化Si，形成由SiO 2组成的纳米氧化物薄膜。

公开(公告)号：US20050182587A1

公开(公告)日：2005-08-18

申请号：US11052908

申请日：2005-02-09

申请人： Yasuo Sato ,  Shuji Hamada ,  Toshiyuki Maeda ,  Atsuo Takatori ,  Yasuyuki Nozuyama

发明人： Yasuo Sato ,  Shuji Hamada ,  Toshiyuki Maeda ,  Atsuo Takatori ,  Yasuyuki Nozuyama

IPC分类号： G01R31/317 ,  G01R31/30 ,  H01L21/66 ,  H01L21/82 ,  G06F19/00

CPC分类号： G01R31/31704 ,  G01R31/3016

摘要： A circuit quality evaluation method obtains an indicator linked to the quality of a circuit by applying information representing a minimum delay margin of a path passing through an assumed fault site, a machine cycle, and a delay fault occurrence frequency. Further, the circuit quality evaluation method evaluates the quality of the circuit based on the indicator.

摘要翻译： 电路质量评估方法通过应用表示通过假定故障位置的路径的最小延迟余量，机器周期和延迟故障发生频率的信息来获得与电路质量相关联的指示符。 此外，电路质量评估方法基于指示器来评估电路的质量。

公开(公告)号：US06922094B2

公开(公告)日：2005-07-26

申请号：US10282862

申请日：2002-10-28

申请人： Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

发明人： Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

IPC分类号： G11C11/417 ,  H03K3/037 ,  H03K3/356 ,  H03K3/3565 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175 ,  H03K3/286

CPC分类号： H03K3/0375 ,  H03K3/356156 ,  H03K3/3565 ,  H03K17/162 ,  H03K17/165 ,  H03K19/00338

摘要： A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be put out, it is corrected by a pull-up path or a pull-down path, and when a soft error occurs in the data in the pull-up path or the pull-down path, the error data in the pull-up path or the pull-down path is prevented from affecting each other, as well as turning off the correcting function to prevent the influence on the data to be put out.