公开(公告)号：US20040053489A1

公开(公告)日：2004-03-18

申请号：US10454530

申请日：2003-06-05

申请人： NGK SPARK PLUG CO., LTD. ,  NEC ELECTRONICS CORPORATION

发明人： Keiichiro Kata ,  Hirokazu Honda ,  Kazuhiro Baba ,  Tadanori Shimoto ,  Katsumi Kikuchi ,  Rokuro Kambe ,  Satoshi Hirano ,  Shinya Miyamoto

IPC分类号： H01L021/4763

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2924/19041 ,  H05K3/0035 ,  H05K3/28 ,  H05K3/4682 ,  H05K2201/2018 ,  H05K2203/0152 ,  H05K2203/0376

摘要： A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.

摘要翻译： 公开了一种制造多层布线基板的方法。 多层布线基板不含芯基板，并且包括包含绝缘体层和布线层的堆积层。 构建层的第一主表面和第二主表面之一形成有金属支撑框体。 该方法包括以下步骤：在金属支撑板的第一主表面上形成第一绝缘体层，其中第一绝缘体层包含在绝缘体层中，并成为位于第一绝缘体层的第一主表面侧的第一抗蚀剂层 并且在第一绝缘体层的第一主表面上的给定位置形成第一金属焊盘层，其中第一金属焊盘层包括在布线层中并且变成金属焊盘层。

公开(公告)号：US20040053446A1

公开(公告)日：2004-03-18

申请号：US10624596

申请日：2003-07-23

申请人： NEC ELECTRONICS CORPORATION

发明人： Yoshihisa Matsubara

IPC分类号： H01L021/44

CPC分类号： H01L21/76858 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/05147 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device is improved in adhesion between: at least a contact portion of its tantalum-base metal serving as a barrier metal film; and, its copper buried wiring brought into contact with the contact portion to prevent the copper buried wiring from peeling off, and is therefore improved in reliability. Formed in a trench designed for a buried wiring of an interlayer insulation film are: a tantalum film having a film thickness of from 200 to 500 angstroms; and, a copper buried wiring having a film thickness of from 1.1 to 1.55 nullm. This copper buried wiring is formed by stacking together a copper thin film having a film thickness of from 0.08 to 0.12 nullm and a copper thick film having a film thickness of from 1.0 to 1.5 nullm. Further formed between the tantalum film and the copper buried wiring is an amorphous metal film having a thickness of approximately angstroms. Still further formed between the tantalum film and each of a surface protection film and an interlayer insulation film is a tantalum oxide film having a film thickness of approximately several angstroms.

摘要翻译： 半导体器件的粘合性提高了至少一个其作为阻挡金属膜的钽基金属的接触部分; 并且其铜埋布线与接触部分接触以防止铜掩埋布线剥离，因此提高了可靠性。 在用于层间绝缘膜的掩埋布线的沟槽中形成的是：膜厚度为200至500埃的钽膜; 以及膜厚为1.1〜1.55μm的铜掩埋布线。 铜掩埋布线通过层叠厚度为0.08〜0.12μm的铜薄膜和膜厚为1.0〜1.5μm的铜厚膜而形成。 在钽膜和铜掩埋布线之间形成的是具有近似埃的厚度的非晶态金属膜。 在钽膜和表面保护膜之间还形成有层间绝缘膜，其膜厚约为几埃的氧化钽膜。

公开(公告)号：US20040048415A1

公开(公告)日：2004-03-11

申请号：US10639580

申请日：2003-08-13

申请人： NEC ELECTRONICS CORPORATION

发明人： Masanao Horie

IPC分类号： H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/97 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

摘要： A first resin coat layer, which electrically insulates LSI pads and first contact electrodes both formed on each of LSI chips separated from one another, is so designed as to extend farther outward from the peripheral edge of the LSI chip, so that the package is made larger than the LSI chip. An intermediate wire layer and some of second contact electrodes are formed on that part of the first resin coat layer which is formed outside the peripheral edge of the LSI chip. CSP pads and CSP bumps are formed on the second contact electrodes. That is, the CSP pads and CSP bumps are formed on portions outside the peripheral edge of the LSI chip. Therefore, the pitches of those external terminals can be made wider than the narrow layout pitches of the LSI pads laid out adjacent to one another. This can facilitate the interconnection design on an external board and the fabrication of the CSP type package.

摘要翻译： 将彼此分离的每个LSI芯片上形成的LSI焊盘和第一接触电极电绝缘的第一树脂涂层设计成从LSI芯片的周边边缘向外延伸，使得封装被制成 大于LSI芯片。 在形成在LSI芯片的周边外侧的第一树脂涂层的部分上形成中间线层和一些第二接触电极。 CSP焊盘和CSP凸点形成在第二接触电极上。 也就是说，CSP焊盘和CSP凸块形成在LSI芯片的外围边缘之外的部分。 因此，这些外部端子的间距可以比彼此相邻布置的LSI焊盘的窄布置间距更宽。 这可以促进外部板上的互连设计和CSP型封装的制造。

公开(公告)号：US20040041641A1

公开(公告)日：2004-03-04

申请号：US10649833

申请日：2003-08-28

申请人： NEC Electronics Corporation

发明人： Kazuhiro Nakajima

IPC分类号： H03B001/00

CPC分类号： G01R31/2884 ,  G01R31/275 ,  H03K3/0315

摘要： A ring oscillator for a test apparatus and method for verifying fabrication of transistors in an integrated circuit on a die under test is implemented. The ring oscillator is fabricated on the die and includes a positive feedback loop between a circuit output terminal and a feedback input terminal. The feedback loop includes a plurality of delaying stages connected in cascade. A transfer gate is coupled to each delaying stage. Each of the transfer gates includes a pair of transistors of the first and second conductivity types connected in parallel. The ring oscillator is operable to provide a first oscillator output signal during a first test mode when the transistors of the first conductivity type are ON and the transistors of the second conductivity type are OFF. The ring oscillator is operable to provide a second oscillator output signal during a second test mode when the transistors of the first conductivity type are OFF and the transistors of the second conductivity type are ON. The ring oscillator is operable to provide a second oscillator output signal during a second test mode when the transistors of the first conductivity type are ON and the transistors of the second conductivity type are ON.

摘要翻译： 实施用于测试装置的环形振荡器和用于验证被测试晶片上的集成电路中的晶体管的制造的方法。 环形振荡器在芯片上制造，并且在电路输出端子和反馈输入端子之间包括正反馈回路。 反馈回路包括级联连接的多个延迟级。 传输门耦合到每个延迟级。 每个传输门包括并联连接的第一和第二导电类型的一对晶体管。 当第一导电类型的晶体管为ON并且第二导电类型的晶体管为截止时，环形振荡器可操作以在第一测试模式期间提供第一振荡器输出信号。 当第一导电类型的晶体管截止并且第二导电类型的晶体管导通时，环形振荡器可操作以在第二测试模式期间提供第二振荡器输出信号。 当第一导电类型的晶体管导通并且第二导电类型的晶体管导通时，环形振荡器可操作以在第二测试模式期间提供第二振荡器输出信号。

公开(公告)号：US20040036076A1

公开(公告)日：2004-02-26

申请号：US10642279

申请日：2003-08-18

申请人： NEC ELECTRONICS CORPORATION

发明人： Koji Arita ,  Masayoshi Tagami ,  Hidenobu Miyamoto

IPC分类号： H01L027/15

CPC分类号： H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

摘要： Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

摘要翻译： 公开了具有精密加工的双镶嵌结构的半导体器件。 半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜，蚀刻停止膜，第二层间膜，第一硬掩模和第二硬掩模而获得的，第二硬掩模形成为具有 沟槽图案。 至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上，使得其整个表面是平坦的。 光致抗蚀剂形成在光吸收牺牲膜上，并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。 使用光致抗蚀剂作为蚀刻掩模，至少吸光牺牲膜，第一硬掩模和第二层间膜被选择性地蚀刻。

公开(公告)号：US20040032779A1

公开(公告)日：2004-02-19

申请号：US10614955

申请日：2003-07-08

申请人： NEC Electronics Corporation

发明人： Takayuki Suzu

IPC分类号： G11C007/00

CPC分类号： G11C8/18 ,  G11C2207/104 ,  G11C2207/105

摘要： A semiconductor memory device is comprised of a plurality of sense amplifiers. The sense amplifiers are arranged in two amplifier columns. The two amplifier columns are disposed between two cell columns of cell plates. An address circuitry, an ATD circuitry, and a delay circuitry are disposed between an input pin row and the two cell columns. An ATD pulse synthesizer Is disposed between the two amplifier columns and spaced a predetermined signal transmission path from the ATD and delay circuitries.

摘要翻译： 半导体存储器件由多个读出放大器组成。 读出放大器布置在两个放大器列中。 两个放大器列设置在两个单元格单元格列之间。 地址电路，ATD电路和延迟电路设置在输入引脚列和两个单元列之间。 ATD脉冲合成器设置在两个放大器列之间，并且与ATD和延迟电路隔开预定的信号传输路径。

公开(公告)号：US20040023483A1

公开(公告)日：2004-02-05

申请号：US10619001

申请日：2003-07-15

申请人： NEC ELECTRONICS CORPORATION

发明人： Yasuaki Tsuchiya ,  Tomoko Inoue

IPC分类号： H01L021/4763 ,  H01L021/44 ,  H01L021/302 ,  H01L021/461

CPC分类号： H01L21/3212

摘要： The present invention relates to a method of manufacturing a semiconductor device, comprising the steps of: forming a sunken section in an insulating film formed on a substrate; forming a barrier metal film on said insulating film inclusive of said sunken section; forming a copper-based film over the entire surface so as to fill up said sunken section; and forming a copper-based metal interconnection, which comprises the step of polishing this substrate surface by the chemical mechanical polishing method, using a polishing slurry containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water, wherein a content ratio of said amino acid to said triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.

摘要翻译： 本发明涉及一种制造半导体器件的方法，包括以下步骤：在形成在衬底上的绝缘膜中形成凹陷部分; 在包括所述下沉部分的所述绝缘膜上形成阻挡金属膜; 在整个表面上形成铜基膜，以便填充所述凹陷部分; 并且形成铜基金属互连，其包括通过化学机械抛光方法使用包含二氧化硅研磨材料，氧化剂，氨基酸，三唑基化合物和水的研磨浆料对该基材表面进行抛光的步骤 其中所述氨基酸与所述三唑类化合物（氨基酸/三唑类化合物（重量比））的含量比为5〜8。

公开(公告)号：US20040021481A1

公开(公告)日：2004-02-05

申请号：US10435112

申请日：2003-05-08

申请人： NEC Electronics Corporation

发明人： Tsuyoshi Ohno

IPC分类号： H03K019/003

CPC分类号： H03K19/0005 ,  H04L25/0278

摘要： A method for producing a stable control signal for impedance matching is provided which is capable of suppressing variation in impedance matching data by adding a shift voltage to a voltage to be compared. A comparator compares the voltage to be compared with a reference voltage and an up-down counter performs a counting operation according to a result from the comparison. A code converting circuit converts a count value output from the up-down counter to a thermometer code used for changing an impedance of an impedance varying circuit. A change in the impedance is made in a manner that, even when the voltage to be compared gets closest to the reference voltage, a shift voltage for the comparator to make an exact comparison is fed to the voltage to be compared. An averaging circuit averages a count value and the code converting circuit converts a resulting average value to the thermometer code.

摘要翻译： 提供一种用于产生用于阻抗匹配的稳定控制信号的方法，其能够通过向要比较的电压添加移位电压来抑制阻抗匹配数据的变化。 比较器将比较电压与参考电压进行比较，升降计数器根据比较结果进行计数操作。 代码转换电路将从升降计数器输出的计数值转换为用于改变阻抗变化电路的阻抗的温度计代码。 阻抗的变化是这样的：即使当待比较的电压最接近参考电压时，比较器进行精确比较的移位电压被馈送到要比较的电压。 平均电路对计数值进行平均，代码转换电路将得到的平均值转换为温度计代码。

公开(公告)号：US20040004455A1

公开(公告)日：2004-01-08

申请号：US10602063

申请日：2003-06-24

申请人： NEC ELECTRONICS CORPORATION ,  NEC CORPORATION

发明人： Hiromitsu Fujimoto ,  Motoharu Nagase

IPC分类号： H02P003/00

CPC分类号： H02P6/20 ,  H02P2203/01

摘要： In a sensorless brushless DC motor formed by a stator including a plurality of windings and a rotor including permanent magnet poles, inductances of the windings are detected while the rotor is stationary, and then, the angle of the stationary rotor is detected in accordance with the detected inductances.

摘要翻译： 在由包括多个绕组的定子和包括永磁体的转子形成的无传感器无刷直流电动机中，在转子静止时检测绕组的电感，然后根据 检测电感。

公开(公告)号：US20040004229A1

公开(公告)日：2004-01-08

申请号：US10606836

申请日：2003-06-27

申请人： NEC Electronics Corporation

发明人： Naoto Akiyama

IPC分类号： H01L029/74 ,  H01L031/111 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC分类号： H01L27/11 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1116

摘要： The semiconductor device includes a plurality of transistors, wherein one of the transistors that has the thinnest gate dielectric layer is selected to serve as a power source protection element, among a plurality of transistors, each having a gate dielectric layer of an independently set film thickness, disposed on a same substrate to be operated by a voltage from a same power source. Also, a threshold voltage of the transistor selected as the power source protection element is set higher than other transistor that also has the thinnest gate dielectric layer.

摘要翻译： 半导体器件包括多个晶体管，其中在多个晶体管中选择具有最薄栅极介电层的晶体管中的一个用作电源保护元件，每个晶体管具有独立设定的膜厚度的栅极介电层 ，设置在同一基板上，由相同电源的电压进行操作。 此外，选择为电源保​​护元件的晶体管的阈值电压被设置为高于也具有最薄栅介电层的其它晶体管。