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公开(公告)号：US20240014286A1
公开(公告)日：2024-01-11
申请号：US18345767
申请日：2023-06-30
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Mario Giuseppe SAGGIO , Cateno Marco CAMALLERI , Alfio GUARNERA
CPC classification number: H01L29/4933 , H01L29/1608 , H01L29/7802 , H01L21/049 , H01L29/66068
Abstract: A power MOSFET device includes a semiconductor body having a first main surface. The semiconductor body includes an active area facing the first main surface. The power MOSFET device includes an isolated-gate structure, which extends over the active area and includes a gate-oxide layer, which is made of insulating material and extends over the first main surface, and a gate region buried in the gate-oxide layer so as to be electrically insulated from the semiconductor body. The gate region includes a gate layer of polysilicon and at least one first silicide electrical-modulation region and one second silicide electrical-modulation region, which extend in the gate layer so as to face a top surface of the gate layer and to be arranged alongside one another and spaced apart from one another in a first plane.
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公开(公告)号：US20240012871A1
公开(公告)日：2024-01-11
申请号：US17859769
申请日：2022-07-07
Inventor： Antonio DE VITA , Thomas BOESCH , Giuseppe DESOLI
CPC classification number: G06F17/15 , G06F7/5443
Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.
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公开(公告)号：US20240006277A1
公开(公告)日：2024-01-04
申请号：US18369652
申请日：2023-09-18
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto ARRIGONI , Giovanni GRAZIOSI , Aurora SANNA
IPC: H01L23/495 , H01L21/48
CPC classification number: H01L23/49589 , H01L21/4825 , H01L23/49503 , H01L23/4952
Abstract: Disclosed herein is a method for manufacturing a semiconductor product package. The method includes arranging a leadframe with one or more leads such that each lead has an inner end facing a portion of a die-pad, attaching a semiconductor chip to the die-pad, attaching a first electrically conductive mass to the die-pad such that it is aligned with the inner end of a lead protruding over the die-pad, attaching an electrical component to the first electrically conductive mass such that a longitudinal axis of the electrical component is arranged traverse to the die-pad, and coupling a second electrically conductive mass between a termination of the electrical component and the inner end of the lead.
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公开(公告)号：US11864361B2
公开(公告)日：2024-01-02
申请号：US16934991
申请日：2020-07-21
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Cristiano Gianluca Stella , Francesco Salamone
IPC: H05K7/20 , H01L23/373 , H01L25/07
CPC classification number: H05K7/209 , H01L23/3735 , H01L25/071
Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
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115.发明公开公开(公告)号：US20230420557A1
公开(公告)日：2023-12-28
申请号：US18335916
申请日：2023-06-15
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Angelo MAGRI' , Stefania FORTUNA
IPC: H01L29/78 , H01L21/265 , H01L21/765 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/66
CPC classification number: H01L29/7813 , H01L21/26513 , H01L21/765 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/66734
Abstract: A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.
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Patent Agency Ranking
公开(公告)号：US20230418559A1
公开(公告)日：2023-12-28
申请号：US17847817
申请日：2022-06-23
Inventor： Michele ROSSI , Thomas BOESCH , Giuseppe DESOLI
Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.
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公开(公告)号：US20230418548A1
公开(公告)日：2023-12-28
申请号：US17846586
申请日：2022-06-22
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco STILGENBAUER
IPC: G06F3/16
CPC classification number: G06F3/165
Abstract: An audio device includes a gain step selection circuit that receives a different requested gain value and an associated requested step size from each of a plurality of sources, compares each requested gain value to a same feedback gain value and generates a polarity based thereupon, performs step polarization on each requested step size as a function of the generated polarity therefor to thereby generate a plurality of step values, and outputs a least of the plurality of step values as an output step value. An accumulator circuit generates a current input gain value based upon the output step value and the feedback gain value, and then updates the feedback gain value to be equal to the current input gain value. A normalizing circuit multiplies an input data value by the current input gain value and applies a truncation function to a result thereof to produce an output data value.
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118.发明授权公开(公告)号：US11855604B2
公开(公告)日：2023-12-26
申请号：US17031181
申请日：2020-09-24
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Federico Vercesi , Lorenzo Corso , Giorgio Allegato , Gabriele Gattere
CPC classification number: H03H9/1021 , B81B7/0038 , B81C1/00285 , H03H3/02 , H03H9/17 , B81B2201/0271 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2207/07 , B81C2201/0105 , B81C2203/0118 , H03H2003/022 , H03H2003/027 , H03H2009/155
Abstract: A microelectromechanical resonator device has: a main body, with a first surface and a second surface, opposite to one another along a vertical axis, and made of a first layer and a second layer, arranged on the first layer; a cap, having a respective first surface and a respective second surface, opposite to one another along the vertical axis, and coupled to the main body by bonding elements; and a piezoelectric resonator structure formed by: a mobile element, constituted by a resonator portion of the first layer, suspended in cantilever fashion with respect to an internal cavity provided in the second layer and moreover, on the opposite side, with respect to a housing cavity provided in the cap; a region of piezoelectric material, arranged on the mobile element on the first surface of the main body; and a top electrode, arranged on the region of piezoelectric material, the mobile element constituting a bottom electrode of the piezoelectric resonator structure.
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公开(公告)号：US11855554B2
公开(公告)日：2023-12-26
申请号：US17819504
申请日：2022-08-12
Applicant: STMicroelectronics S.r.l.
Inventor： Michele Boscolo Berto , Ezio Galbiati
Abstract: A method of driving an electrical load includes coupling a power supply source to a power supply pin of a driver circuit, and coupling an electrical load to at least one output pin of the driver circuit. A driver sub-circuit of the driver circuit produces at least one driving signal for driving the electrical load. The at least one driving signal is provided to the electrical load via the at least one output pin. The at least one driving signal is modulated to supply the electrical load with a load current and to subsequently interrupt the load current. A compensation current pulse is sunk from the power supply pin, at a compensation circuit of the driver circuit, in response to the load current being interrupted.
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120.发明公开公开(公告)号：US20230409320A1
公开(公告)日：2023-12-21
申请号：US18325519
申请日：2023-05-30
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Giuseppe Fontana , Giuseppe Guarnaccia , Stefano Catalano
IPC: G06F9/30
CPC classification number: G06F9/3004 , G06F9/30116 , G06F9/30189
Abstract: In an embodiment a One-Time Programmable (OTP) memory controller includes a data register, a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area, a communication interface configured to receive a read request requesting the data of a given memory slot and a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase.
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