中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

248 records (took 0.03 seconds)

    Radical-component oxide etch
    111.
    发明授权
    Radical-component oxide etch 有权

    公开(公告)号：US09437451B2

    公开(公告)日：2016-09-06

    申请号：US14703333

    申请日：2015-05-04

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun Chen ,  Jingchun Zhang ,  Ching-Mei Hsu ,  Seung Park ,  Anchuan Wang ,  Nitin K. Ingle

    IPC: H01L21/302 ,  H01L21/311

    CPC classification number: H01L21/31116 ,  H01J37/32357

    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.

    Dry-etch selectivity
    112.
    发明授权
    Dry-etch selectivity 有权

    公开(公告)号：US09384997B2

    公开(公告)日：2016-07-05

    申请号：US14602835

    申请日：2015-01-22

    Applicant: Applied Materials, Inc.

    Inventor： He Ren ,  Jang-Gyoo Yang ,  Jonghoon Baek ,  Anchuan Wang ,  Soonam Park ,  Saurabh Garg ,  Xinglong Chen ,  Nitin K. Ingle

    IPC: H01L21/302 ,  H01L21/311 ,  H01J37/32

    CPC classification number: H01L21/31116 ,  H01J37/32357

    Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.

    V trench dry etch
    113.
    发明授权
    V trench dry etch 有权
    V沟干蚀刻

    公开(公告)号：US09355856B2

    公开(公告)日：2016-05-31

    申请号：US14485551

    申请日：2014-09-12

    Applicant: Applied Materials, Inc.

    Inventor： Xikun Wang ,  Anchuan Wang ,  Nitin K. Ingle

    IPC: H01L21/302 ,  H01L21/3065

    CPC classification number: H01L21/3065 ,  H01J37/32357

    Abstract: Methods of producing V-shaped trenches in crystalline substrates are described. The methods involve processing a patterned substrate with etch masking materials defining each side of exposed silicon (100). The exposed silicon (100) is exposed to remotely-excited halogen-containing precursor including chlorine or bromine. The plasma effluents formed from the halogen-containing precursor preferentially remove silicon from all exposed facets other than silicon (111). Etching the crystalline substrates with the plasma effluents produce at least two silicon (111) facets between two adjacent masking elements. Forming the silicon (111) facets may be accelerated by pretreating the crystalline substrates using a halogen-containing precursor locally excited in a biased plasma to initiate the generation of the trench.

    Abstract translation: 描述了在晶体衬底中生产V形沟槽的方法。 该方法涉及用限定暴露的硅（100）的每一侧的蚀刻掩模材料来处理图案化衬底。 暴露的硅（100）暴露于包含氯或溴的远红外含卤素前体。 由含卤素的前体形成的等离子体流出物优先从除硅（111）以外的所有暴露面除去硅。 用等离子体流出物蚀刻晶体衬底在两个相邻的掩模元件之间产生至少两个硅（111）刻面。 可以通过使用在偏压等离子体中局部激发的含卤素前体来预处理晶体衬底来开始形成硅（111）刻面，以开始产生沟槽。

    Oxide and metal removal
    114.
    发明授权
    Oxide and metal removal 有权
    氧化物和金属去除

    公开(公告)号：US09309598B2

    公开(公告)日：2016-04-12

    申请号：US14288696

    申请日：2014-05-28

    Applicant: Applied Materials, Inc.

    Inventor： Xikun Wang ,  Jie Liu ,  Anchuan Wang ,  Nitin K. Ingle ,  Jeffrey W. Anthis ,  Benjamin Schmiege

    IPC: C03C15/00 ,  C23F1/12 ,  H01J37/32 ,  H01L21/3213

    CPC classification number: C23F1/12 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J2237/327 ,  H01J2237/334 ,  H01J2237/3341 ,  H01L21/32135 ,  H01L21/32138

    Abstract: Methods are described herein for etching metal films which are difficult to volatize. The methods include exposing a metal film to a chlorine-containing precursor (e.g. Cl2). Chlorine is then removed from the substrate processing region. A carbon-and-nitrogen-containing precursor (e.g. TMEDA) is delivered to the substrate processing region to form volatile metal complexes which desorb from the surface of the metal film. The methods presented remove metal while very slowly removing the other exposed materials. A thin metal oxide layer may be present on the surface of the metal layer, in which case a local plasma from hydrogen may be used to remove the oxygen or amorphize the near surface region, which has been found to increase the overall etch rate.

    Abstract translation: 本文描述了用于蚀刻难以挥发的金属膜的方法。 这些方法包括将金属膜暴露于含氯前体（例如Cl 2）。 然后从基板处理区域除去氯。 将含碳和氮的前体（例如TMEDA）输送到基底加工区域以形成从金属膜的表面解吸的挥发性金属络合物。 所提供的方法去除金属，同时非常缓慢地除去其它暴露的材料。 金属层的表面上可能存在薄的金属氧化物层，在这种情况下，可以使用来自氢的局部等离子体来除去氧或使近表面区域非晶化，这已经被发现增加了整个蚀刻速率。

    V TRENCH DRY ETCH
    115.
    发明申请
    V TRENCH DRY ETCH 有权

    公开(公告)号：US20160079072A1

    公开(公告)日：2016-03-17

    申请号：US14485551

    申请日：2014-09-12

    Applicant: Applied Materials, Inc.

    Inventor： Xikun Wang ,  Anchuan Wang ,  Nitin K. Ingle

    IPC: H01L21/3065

    CPC classification number: H01L21/3065 ,  H01J37/32357

    Abstract: Methods of producing V-shaped trenches in crystalline substrates are described. The methods involve processing a patterned substrate with etch masking materials defining each side of exposed silicon (100). The exposed silicon (100) is exposed to remotely-excited halogen-containing precursor including chlorine or bromine. The plasma effluents formed from the halogen-containing precursor preferentially remove silicon from all exposed facets other than silicon (111). Etching the crystalline substrates with the plasma effluents produce at least two silicon (111) facets between two adjacent masking elements. Forming the silicon (111) facets may be accelerated by pretreating the crystalline substrates using a halogen-containing precursor locally excited in a biased plasma to initiate the generation of the trench.

    Abstract translation: 描述了在晶体衬底中生产V形沟槽的方法。 该方法涉及用限定暴露的硅（100）的每一侧的蚀刻掩模材料来处理图案化衬底。 暴露的硅（100）暴露于包含氯或溴的远红外含卤素前体。 由含卤素的前体形成的等离子体流出物优先从除硅（111）以外的所有暴露面除去硅。 用等离子体流出物蚀刻晶体衬底在两个相邻的掩模元件之间产生至少两个硅（111）刻面。 可以通过使用在偏压等离子体中局部激发的含卤素前体来预处理晶体衬底来开始形成硅（111）刻面，以开始产生沟槽。

    INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN
    116.
    发明申请
    INTEGRATED BIT-LINE AIRGAP FORMATION AND GATE STACK POST CLEAN 有权
    集成的位线空气格栅和门盖清洗

    公开(公告)号：US20160035614A1

    公开(公告)日：2016-02-04

    申请号：US14448059

    申请日：2014-07-31

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

    IPC: H01L21/764 ,  H01L29/06 ,  H01L21/311 ,  H01L29/49 ,  H01L21/02 ,  H01L27/115

    CPC classification number: H01L21/764 ,  H01J37/32357 ,  H01L21/02071 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/68764 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66833 ,  H01L29/7887

    Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

    Abstract translation: 描述形成闪速存储器单元的方法，其包括用于改善性能的气隙。 这些方法对于所谓的“2-d平坦单元”闪存架构是有用的。 2-d平板电池闪存包括反应离子蚀刻，以将沟槽挖掘成包含高功函数和其它金属层的多层。 本文描述的方法从多层沟槽的侧壁去除金属氧化物碎屑，然后在不破坏真空的情况下选择性地去除成为气隙的浅沟槽隔离（STI）氧化。 金属氧化物去除和STI氧化去除都是使用远程激发的氟等离子体流出物，在相同的主机中进行高选择性蚀刻工艺。

    HIGH SELECTIVITY GAS PHASE SILICON NITRIDE REMOVAL
    118.
    发明申请
    HIGH SELECTIVITY GAS PHASE SILICON NITRIDE REMOVAL 审中-公开
    高选择性气相氮化硅去除

    公开(公告)号：US20150371865A1

    公开(公告)日：2015-12-24

    申请号：US14308978

    申请日：2014-06-19

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun Chen ,  Nitin K. Ingle ,  Anchuan Wang

    IPC: H01L21/311 ,  C09K13/08

    CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01J37/3244

    Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a gas phase etch using partial remote plasma excitation. The remote plasma excites a fluorine-containing precursor and the plasma effluents created are flowed into a substrate processing region. A hydrogen-containing precursor, e.g. water, is concurrently flowed into the substrate processing region without plasma excitation. The plasma effluents are combined with the unexcited hydrogen-containing precursor in the substrate processing region where the combination reacts with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while retaining silicon, such as polysilicon.

    Abstract translation: 描述了在图案化异质结构上蚀刻氮化硅的方法，并且包括使用部分远程等离子体激发的气相蚀刻。 远程等离子体激发含氟前体，产生的等离子体流出物流入基板处理区域。 含氢前体，例如 水同时流入基板处理区域而没有等离子体激发。 等离子体流出物与组合与氮化硅反应的衬底处理区域中的不含氢的前体组合。 等离子体流出物与图案化的异质结构反应以选择性地去除氮化硅，同时保留硅，例如多晶硅。

    Doped silicon oxide etch
    119.
    发明授权
    Doped silicon oxide etch 有权
    掺杂氧化硅蚀刻

    公开(公告)号：US09202708B1

    公开(公告)日：2015-12-01

    申请号：US14523647

    申请日：2014-10-24

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun Chen ,  Sang-jin Kim ,  Anchuan Wang ,  Nitin K. Ingle

    IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

    CPC classification number: H01L21/31116 ,  H01J37/32357

    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove two separate regions of silicon oxide at distinct etch rates. The methods may be used to remove doped silicon oxide faster than undoped silicon oxide or more lightly-doped silicon oxide. The relative humidity in the substrate processing region may be low during the etch process to increase the etch selectivity of the doped silicon oxide.

    Abstract translation: 描述了在图案化的异质结构上蚀刻暴露的氧化硅的方法，并且包括使用在远程等离子体中形成的等离子体流出物的气相蚀刻。 远程等离子体与含氧前体组合起来激发含氟前体。 远程等离子体内的等离子体流出物流入基板处理区域，其中等离子体流出物与水蒸汽或醇组合。 该组合与图案化的异质结构反应以以不同的蚀刻速率去除两个分离的氧化硅区域。 该方法可以用于比未掺杂的氧化硅或更多的轻掺杂的氧化硅更快地除去掺杂的氧化硅。 在蚀刻工艺期间，衬底处理区域中的相对湿度可能较低，以增加掺杂氧化硅的蚀刻选择性。

Patent Agency Ranking