公开(公告)号：US06667533B2

公开(公告)日：2003-12-23

申请号：US09684000

申请日：2002-03-11

申请人： Timothy H. Daubenspeck ,  Thomas L. McDevitt ,  William T. Motsiff ,  Anthony K. Stamper

发明人： Timothy H. Daubenspeck ,  Thomas L. McDevitt ,  William T. Motsiff ,  Anthony K. Stamper

IPC分类号： H01L2900

CPC分类号： H01L23/53295 ,  H01L23/5256 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.

公开(公告)号：US08957531B2

公开(公告)日：2015-02-17

申请号：US13277246

申请日：2011-10-20

申请人： William E. Bernier ,  Timothy H. Daubenspeck ,  Virendra R. Jadhav ,  Valerie A. Oberson ,  David L. Questad

发明人： William E. Bernier ,  Timothy H. Daubenspeck ,  Virendra R. Jadhav ,  Valerie A. Oberson ,  David L. Questad

IPC分类号： H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  G01N3/60 ,  G01N19/04

CPC分类号： H01L22/30 ,  B05D1/36 ,  G01N3/60 ,  G01N19/04 ,  G01N25/16 ,  G01N2203/0296 ,  G01N2203/0298 ,  H01L24/13 ,  H01L2224/131 ,  H01L2924/10253 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

摘要： A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.

摘要翻译： 公开了一种对称的平板层压结构，用于使测试结构中的变量最小化，以实验测量白色凸起对CTE不匹配的敏感性。 测试结构包括平板层压结构。 使用测试结构的方法包括隔离多变量芯片连接问题的原因，其由翘曲不利地影响并量化翘曲的贡献本身在多变量芯片连接问题的形成中。

公开(公告)号：US08415260B2

公开(公告)日：2013-04-09

申请号：US12756284

申请日：2010-04-08

申请人： Albert J. Banach ,  Timothy H. Daubenspeck ,  Wolfgang Sauter

发明人： Albert J. Banach ,  Timothy H. Daubenspeck ,  Wolfgang Sauter

IPC分类号： H01L21/00

CPC分类号： H01L23/544 ,  H01L21/56 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

摘要翻译： 提供了有机层压包装的芯片识别和制造方法。 该方法包括在包括多个芯片的晶片上形成材料。 该方法还包括修改材料以为晶片上的多个芯片中的每一个提供唯一的识别。 有机层压结构包括具有装置的芯片和放置在芯片上的材料，其被修改为具有用于芯片的唯一识别标记。

公开(公告)号：US20110298095A1

公开(公告)日：2011-12-08

申请号：US12796068

申请日：2010-06-08

申请人： Timothy H. Daubenspeck ,  Ekta Misra ,  Marie-Claude Paquet ,  Francis Santerre ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Ekta Misra ,  Marie-Claude Paquet ,  Francis Santerre ,  Wolfgang Sauter

IPC分类号： H01L21/78 ,  H01L23/00

CPC分类号： H01L21/78 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate.

摘要翻译： 本发明的实施例提供了具有沿着半导体衬底的表面延伸到半导体衬底的边缘的钝化层的半导体芯片及其形成方法。 本发明的一个方面提供一种半导体芯片，包括：半导体衬底; 钝化层，包括沿半导体衬底的表面设置并延伸到半导体衬底的至少一个边缘的光敏聚酰亚胺; 以及延伸穿过钝化层到半导体衬底的表面的沟道。

公开(公告)号：US07863183B2

公开(公告)日：2011-01-04

申请号：US11306983

申请日：2006-01-18

申请人： Timothy H. Daubenspeck ,  William F. Landers ,  Donna S. Zupanski-Nielsen

发明人： Timothy H. Daubenspeck ,  William F. Landers ,  Donna S. Zupanski-Nielsen

IPC分类号： H01L21/4763

CPC分类号： H01L21/288 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05575 ,  H01L2224/05599 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/01015

摘要： The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.

摘要翻译： 本发明涉及一种用于制造具有基本上不含铝的最后一级铜对C4连接的半导体器件的方法。 具体地说，最后一级的铜对C4连接包括含有CoWP，NiMoP，NiMoB，NiReP，NiWP及其组合的界面盖结构。 优选地，界面帽结构包括至少一个CoWP层。 这种CoWP层可以通过选择性无电镀方法容易地在最后一级铜互连上形成。

公开(公告)号：US20090218688A1

公开(公告)日：2009-09-03

申请号：US12039134

申请日：2008-02-28

申请人： Stephen P. Ayotte ,  Timothy H. Daubenspeck ,  Jeffrey Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter

发明人： Stephen P. Ayotte ,  Timothy H. Daubenspeck ,  Jeffrey Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L23/52

CPC分类号： H01L24/11 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05599

摘要： A semiconductor structure includes at least one bond pad. An insulator layer is on the surface of the semiconductor chip and on a portion of the bond pad. The polyimide layer comprises a bottom surface contacting and coplanar with the surface of the semiconductor chip, a top surface opposite and parallel to the bottom surface of the polyimide layer, and a sloped side between corresponding ends of the top surface of the polyimide layer and the bottom surface of the polyimide layer. The sloped side joins the bottom surface of the polyimide layer at the top surface of the bond pad. The sloped side of the polyimide layer forms an angle less than 50° with the bottom surface of the polyimide layer.

摘要翻译： 半导体结构包括至少一个接合焊盘。 绝缘体层位于半导体芯片的表面上和接合焊盘的一部分上。 聚酰亚胺层包括与半导体芯片的表面接触和共面的底表面，与聚酰亚胺层的底表面相反并平行的顶表面，以及在聚酰亚胺层的顶表面的相应端之间的倾斜侧和 聚酰亚胺层的底面。 倾斜侧在接合焊盘的顶表面处连接聚酰亚胺层的底表面。 聚酰亚胺层的倾斜侧与聚酰亚胺层的底面形成小于50°的角度。

公开(公告)号：US07479447B2

公开(公告)日：2009-01-20

申请号：US11277398

申请日：2006-03-24

申请人： Timothy H. Daubenspeck ,  Christopher D. Muzzy ,  Paul S. McLaughlin ,  Judith A. Wright ,  Jean E. Wynne ,  Dae Young Jung

发明人： Timothy H. Daubenspeck ,  Christopher D. Muzzy ,  Paul S. McLaughlin ,  Judith A. Wright ,  Jean E. Wynne ,  Dae Young Jung

IPC分类号： H01L21/44 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A crack stop void is formed in a low-k dielectric layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The crack stop void is formed simultaneously with the formation of an interconnect structure.

摘要翻译： 在相邻熔丝结构之间的低k电介质层中形成裂纹阻挡空隙，用于在保险丝熔断操作期间防止相邻熔丝结构之间的裂纹传播。 裂缝停止空隙与形成互连结构同时形成。

公开(公告)号：US07348210B2

公开(公告)日：2008-03-25

申请号：US10908084

申请日：2005-04-27

申请人： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

发明人： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

IPC分类号： H01L21/00

CPC分类号： H01L23/556 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014

摘要： A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.

摘要翻译： 一种结构及其形成方法。 该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层 其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境 执行钝化层。

公开(公告)号：US06498385B1

公开(公告)日：2002-12-24

申请号：US09388314

申请日：1999-09-01

申请人： Timothy H. Daubenspeck ,  Daniel C. Edelstein ,  Robert M. Geffken ,  William T. Motsiff ,  Anthony K. Stamper ,  Steven H. Voldman

发明人： Timothy H. Daubenspeck ,  Daniel C. Edelstein ,  Robert M. Geffken ,  William T. Motsiff ,  Anthony K. Stamper ,  Steven H. Voldman

IPC分类号： H01L2900

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/76843 ,  H01L23/5258 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.

摘要翻译： 公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。 使用镶嵌工艺完成制作。 金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面 在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。 金属结构可用作耐腐蚀保险丝。 金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。 电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。 电阻器结构可以形成在电介质槽的壁上。 该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。 电阻可以与MOSFET或其他结构串联。

公开(公告)号：US06375159B2

公开(公告)日：2002-04-23

申请号：US09302915

申请日：1999-04-30

申请人： Timothy H. Daubenspeck ,  William T. Motsiff

发明人： Timothy H. Daubenspeck ,  William T. Motsiff

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy. Fabrication methods for providing overlaying material to the entire fuse link line, or to selective portions of the fuse link line are presented.

摘要翻译： 高激光吸收铜熔丝可以最大限度地减少删除导体熔丝部分所需的激光能量。 重要的是，这种类型的熔丝结构将允许形成铜熔丝，其主要通过增加在给定的入射激光能量下的熔丝链的吸收而以明显较少的入射能量被删除。一种金属布线包含熔丝链节段，其中 熔丝链段由至少两个金属的叠层组成。 金属叠层中的底层材料是主电铜导体，并且叠层金属，以及组成中的主导体钨或钛 - 钨的电导体具有预定的厚度和光学性质，使得覆盖金属与 底层金属为入射的红外能量提供了高吸收特性。提供了将覆盖材料提供给整个熔丝连接线或熔丝连接线的选择性部分的制造方法。