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    Methods for selectively removing a fin when forming FinFET devices
    111.
    发明授权
    Methods for selectively removing a fin when forming FinFET devices 有权
    在形成FinFET器件时选择性地去除鳍片的方法

    公开(公告)号：US09337101B1

    公开(公告)日：2016-05-10

    申请号：US14674549

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min Gyu Sung ,  Hoon Kim ,  Chanro Park ,  Ruilong Xie

    IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3065

    CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823481

    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fins in a semiconducting substrate, each of which has a corresponding masking layer feature positioned thereabove, forming a masking layer that has an opening that exposes at least two fins of the plurality of fins, performing an angled etching process through the opening in the masking layer so as to remove the masking layer feature formed above one of the at least two exposed fins, and thereby define an exposed fin, while leaving the masking layer feature intact above the other of the at least two exposed fins, and performing an anisotropic etching process through the opening in the masking layer to remove the exposed fin while leaving the other of the at least two exposed fins intact.

    Abstract translation: 本文中公开的一种说明性方法包括在半导体衬底中形成多个翅片，每个鳍状物具有位于其上方的对应掩模层特征，形成掩模层，掩模层具有暴露至少两个散热片的开口 的翅片，通过掩模层中的开口进行成角度的蚀刻工艺，以去除在至少两个暴露的翅片之一上形成的掩模层特征，从而限定出露出的翅片，同时将掩模层特征保留在 至少两个暴露的翅片中的另一个，并且通过掩模层中的开口进行各向异性蚀刻处理以去除暴露的翅片，同时保持至少两个暴露的翅片中的另一个。

    Methods of fabricating semiconductor fin structures
    112.
    发明授权
    Methods of fabricating semiconductor fin structures 有权
    制造半导体鳍片结构的方法

    公开(公告)号：US09236309B2

    公开(公告)日：2016-01-12

    申请号：US14687300

    申请日：2015-04-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Chanro Park ,  Steven Bentley

    IPC: H01L21/20 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165 ,  H01L29/161

    CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/161 ,  H01L29/165

    Abstract: Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.

    Abstract translation: 提供制造一个或多个半导体鳍片结构的方法，其包括：提供包括第一半导体材料的衬底结构; 在所述衬底结构上方提供散热片堆叠，所述散热片堆叠包括至少一个包括第二半导体材料的半导体层; 在所述散热片堆叠和所述基板结构上沉积保形膜; 以及使用至少部分地将所述散热片堆叠作为掩模来蚀刻所述衬底结构，以便于限定所述一个或多个半导体鳍片结构。 共形保护膜在蚀刻衬底结构期间保护散热片堆叠的至少一个半导体层的侧壁免受蚀刻。 作为一个示例，第一半导体材料可以是或包括硅，第二半导体材料可以是或包括硅锗，并且在一个示例中，保形膜可以是氮化硅。

    Methods of forming gate structures of semiconductor devices
    113.
    发明授权
    Methods of forming gate structures of semiconductor devices 有权
    形成半导体器件栅极结构的方法

    公开(公告)号：US09178035B1

    公开(公告)日：2015-11-03

    申请号：US14459446

    申请日：2014-08-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

    IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3213

    CPC classification number: H01L29/66545 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/4966 ,  H01L29/7833

    Abstract: One method of forming replacement gate structures for first and second devices, the first device being a short channel device and the second device being a long channel device, is disclosed which includes forming a first and a second gate cavity above a semiconductor substrate, the first gate cavity being narrower than the second gate cavity, forming a bulk metal layer within the first and second gate cavities, performing an etching process to recess the bulk metal layer within the first and second gate cavities, resulting in the bulk metal layer within the second gate cavity being at its final thickness, forming a masking layer over the bulk metal layer within the second gate cavity, and performing an etching process to further recess the bulk metal layer within the first gate cavity, resulting in the bulk metal layer within the first gate cavity being at its final thickness.

    Abstract translation: 公开了一种形成第一和第二器件的替代栅极结构的方法，第一器件是短沟道器件，第二器件是长沟道器件，其包括在半导体衬底上形成第一和第二栅极腔，第一器件 栅极腔比第二栅极腔窄，在第一和第二栅极空腔内形成体金属层，执行蚀刻工艺以使第一和第二栅极空腔内的体金属层凹陷，导致第二栅极腔内的体金属层 栅极腔处于其最终厚度，在第二栅极腔内的体金属层上形成掩模层，并且执行蚀刻工艺以进一步使第一栅极腔内的体金属层凹陷，导致第一栅极腔内的主体金属层 门腔处于其最终厚度。

    Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
    114.
    发明授权
    Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes 有权
    用于制造具有金属栅电极的集成电路的集成电路和方法

    公开(公告)号：US08835244B2

    公开(公告)日：2014-09-16

    申请号：US13773397

    申请日：2013-02-21

    Applicant: GlobalFoundries, Inc. ,  International Business Machines Corporation

    Inventor： Ruilong Xie ,  Chanro Park ,  Shom Ponoth

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/788

    CPC classification number: H01L29/66477 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/788

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底上提供牺牲栅极结构。 牺牲栅极结构在两个间隔物之间​​包括两个间隔物和牺牲栅极材料。 该方法将牺牲栅极材料的一部分凹入两个间隔物之间​​。 在使用牺牲栅极材料作为掩模的同时蚀刻两个间隔物的上部区域。 该方法包括去除牺牲栅极材料的剩余部分并暴露两个间隔物的下部区域。 第一金属沉积在两个间隔物的下部区域之间。 第二金属沉积在两个间隔物的上部区域之间。

    INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICES
    119.
    发明申请
    INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200152512A1

    公开(公告)日：2020-05-14

    申请号：US16185015

    申请日：2018-11-09

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Andre P. Labonte ,  Catherine B Labelle ,  Chanro Park

    IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311

    Abstract: A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.

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