公开(公告)号：US11088279B2

公开(公告)日：2021-08-10

申请号：US16783011

申请日：2020-02-05

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Shogo Mochizuki ,  Juntao Li

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/108

Abstract: Techniques for forming VTFET devices with tensile- and compressively-strained channels using dummy stressor materials are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source and drains at a base of the fins; forming bottom spacers on the bottom source and drains; growing at least one dummy stressor material along sidewalls of the fins above the bottom spacers configured to induce strain in the fins; surrounding the fins with a rigid fill material; removing the at least one dummy stressor material to form gate trenches in the rigid fill material while maintaining the strain in the fins by the rigid fill material; forming replacement gate stacks in the gate trenches; forming top spacers on the replacement gate stacks; and forming top source and drains over the top spacers at tops of the fins. A VTFET device is also provided.

公开(公告)号：US11081567B2

公开(公告)日：2021-08-03

申请号：US15918548

申请日：2018-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Choonghyun Lee ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Heng Wu

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/3065

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

公开(公告)号：US11081404B2

公开(公告)日：2021-08-03

申请号：US16400564

申请日：2019-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Alexander Reznicek ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L21/84 ,  H01L29/16 ,  H01L29/78 ,  H01L29/04 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/08

Abstract: A method of forming a nanosheet device is provided. The method includes forming two amorphous source/drain fills on a substrate and one or more semiconductor nanosheet layers between the two amorphous source/drain fills. The method further includes forming a gate dielectric layer on exposed portions of the one or more semiconductor nanosheet layers. The method further includes forming a protective capping layer on the gate dielectric layer, and subjecting the two amorphous source/drain fills to a recrystallization treatment to cause a phase change from the amorphous state to a single crystal or poly-crystalline phase.

公开(公告)号：US11038064B2

公开(公告)日：2021-06-15

申请号：US16744566

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/205 ,  H01L29/66 ,  H01L29/16

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures.

公开(公告)号：US11037832B2

公开(公告)日：2021-06-15

申请号：US16425398

申请日：2019-05-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of forming the same include partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers are etched away. The first inner spacer sub-layer is etched away. A gate stack is formed on and around the channel layers and in contact with the second inner spacer sub-layer.

公开(公告)号：US11031295B2

公开(公告)日：2021-06-08

申请号：US16429371

申请日：2019-06-03

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Kangguo Cheng ,  Ruilong Xie ,  Choonghyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/78 ,  H01L21/311 ,  H01L29/66

Abstract: Embodiments of the present invention are directed to a gate cap last process for forming a self-aligned contact. This gate cap last process allows for a thin SAC cap, as the SAC cap only needs to prevent a short between the metallization contact and the gate. In a non-limiting embodiment of the invention, a gate is formed over a channel region of a fin. The gate can include a gate spacer. A sacrificial contact is formed on a top surface of a source or drain (S/D) region of a substrate. The sacrificial contact is positioned directly adjacent to a sidewall of the gate spacer. An exposed surface of the gate is recessed to form a recessed gate surface and a self-aligned contact (SAC) cap is formed on the recessed gate surface. The sacrificial contact is replaced with a S/D contact.

公开(公告)号：US20210126018A1

公开(公告)日：2021-04-29

申请号：US16662865

申请日：2019-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L27/12 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

公开(公告)号：US20210118998A1

公开(公告)日：2021-04-22

申请号：US17134731

申请日：2020-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shogo Mochizuki ,  Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li

IPC: H01L29/161 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/49

Abstract: A method for forming the semiconductor device that includes forming an etch mask covering a drain side of the gate structure and the silicon containing fin structure; etching a source side of the silicon containing fin structure adjacent to the channel region; and forming a germanium containing semiconductor material on an etched sidewall of the silicon containing fin structure adjacent to the channel region. Germanium from the germanium containing semiconductor material is diffused into the channel region to provide a graded silicon germanium region in the channel region having germanium present at a highest concentration in the channel region at the source end of the channel region and a germanium deficient concentration at the drain end of the channel region.

公开(公告)号：US10971593B2

公开(公告)日：2021-04-06

申请号：US16442047

申请日：2019-06-14

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee ,  Jingyun Zhang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02

Abstract: A p-type FinFET has an oxygen reservoir disposed on the gate stack. The oxygen reservoir provides an oxygen rich environment during processing steps of manufacturing the device to help the work function metal retain or obtain oxygen to maintain or increase the work function and keep the Vth of the device lower.

公开(公告)号：US10971407B2

公开(公告)日：2021-04-06

申请号：US16432346

申请日：2019-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Choonghyun Lee ,  Pouya Hashemi ,  Jingyun Zhang

IPC: H01L21/8228 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/28 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.