公开(公告)号：US20210043755A1

公开(公告)日：2021-02-11

申请号：US17080458

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L27/108 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/11 ,  H01L29/778

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20200335635A1

公开(公告)日：2020-10-22

申请号：US16957617

申请日：2018-03-22

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/786 ,  H01L29/423

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

公开(公告)号：US20200303502A1

公开(公告)日：2020-09-24

申请号：US16361861

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Mark T. BOHR ,  Tahir GHANI ,  Biswajeet GUHA

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

公开(公告)号：US20200219997A1

公开(公告)日：2020-07-09

申请号：US16238978

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA ,  Biswajeet GUHA

IPC: H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

公开(公告)号：US20200098874A1

公开(公告)日：2020-03-26

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin WEBER ,  Harold KENNEL ,  Abhishek SHARMA ,  Christopher JEZEWSKI ,  Matthew V. METZ ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Van H. LE ,  Arnab SEN GUPTA

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L29/267 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L21/322

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006504A1

公开(公告)日：2020-01-02

申请号：US16022502

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Biswajeet GUHA ,  Anand MURTHY ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.

公开(公告)号：US20200006332A1

公开(公告)日：2020-01-02

申请号：US16024671

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Stephen CEA ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/267 ,  H01L29/08

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US20190252525A1

公开(公告)日：2019-08-15

申请号：US16396088

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/7782 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20190148378A1

公开(公告)日：2019-05-16

申请号：US16242946

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Anand S. MURTHY ,  Tahir GHANI ,  Willy RACHMADY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Glenn A. GLASS

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/205 ,  H01L29/423 ,  H01L21/8258 ,  H01L29/10

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

公开(公告)号：US20180277593A1

公开(公告)日：2018-09-27

申请号：US15959027

申请日：2018-04-20

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Tahir GHANI ,  Joseph M. STEIGERWALD ,  John H. EPPLE ,  Yih WANG

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12 ,  H05K999/99

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.