公开(公告)号：US20100128521A1

公开(公告)日：2010-05-27

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US07632749B1

公开(公告)日：2009-12-15

申请号：US10823970

申请日：2004-04-13

申请人： Hiroyuki Ogawa ,  Yider Wu ,  Nian Yang ,  Kuo-Tung Chang ,  Yu Sun

发明人： Hiroyuki Ogawa ,  Yider Wu ,  Nian Yang ,  Kuo-Tung Chang ,  Yu Sun

IPC分类号： H01L21/44

CPC分类号： H01L21/76816 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14

摘要： A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

摘要翻译： 公开并提供了半导体器件。 半导体器件包括具有周边区域和中心区域的焊盘金属层。 此外，半导体器件具有在焊盘金属层的中心区域下方具有多个孔的下部金属层。 此外，在焊盘金属层和下金属层之间形成层间电介质。 在一个实施例中，半导体器件还包括形成在层间电介质中的多个通孔。 通孔电连接焊盘金属层和下部金属层。 另外，通孔位于垫金属层的周边区域的下方。

公开(公告)号：US20090147589A1

公开(公告)日：2009-06-11

申请号：US11953689

申请日：2007-12-10

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/18

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US20090061650A1

公开(公告)日：2009-03-05

申请号：US11847507

申请日：2007-08-30

申请人： Chungho Lee ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Huaqiang Wu ,  Fred Cheung

发明人： Chungho Lee ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Huaqiang Wu ,  Fred Cheung

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/3185 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7923

摘要： Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

摘要翻译： 提供了在存储单元的电荷存储材料层周围形成顶部氧化物的方法以及提高存储单元的电荷存储材料层周围的顶部氧化物的质量的方法。 该方法可以包括在半导体衬底上提供电荷存储层，电荷存储层上的氮化物层和氮化物层上的第一多晶硅层，并将氮化物层的至少一部分转化为顶部氧化物。 通过将氮化物层的至少一部分转化为顶部氧化物层，可以提高所得顶部氧化物层的质量。

公开(公告)号：US07489560B2

公开(公告)日：2009-02-10

申请号：US11398414

申请日：2006-04-05

申请人： Kuo-Tung Chang ,  Timothy Thurgate

发明人： Kuo-Tung Chang ,  Timothy Thurgate

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C5/146 ,  G11C16/04 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a negative substrate bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. The negative substrate bias voltage also reduces the occurrence of program disturbs in cells adjacent to target cells by extending the depletion region deeper below the bit line that corresponds to the drain of the target device. The negative substrate bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce error in the verification operations.

摘要翻译： 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被负极衬底偏置电压偏置以减少或消除否则可能通过目标存储器单元传导的漏电流。 负衬底偏置电压还通过将耗尽区域延伸到对应于目标器件的漏极的位线下方来减少在与目标单元相邻的单元中的编程干扰的发生。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将负的衬底偏置电压施加到目标存储器单元，以减少或消除否则在验证操作中引入错误的泄漏电流。

公开(公告)号：US20080150042A1

公开(公告)日：2008-06-26

申请号：US11958254

申请日：2007-12-17

申请人： Simon Siu-Sing Chan ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Angela T. Hui

发明人： Simon Siu-Sing Chan ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Angela T. Hui

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521

摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.

摘要翻译： 提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞 外部掺杂区域和阻挡金属层。

公开(公告)号：US20080144396A1

公开(公告)日：2008-06-19

申请号：US11612863

申请日：2006-12-19

申请人： Kuo-Tung Chang ,  Wei Zheng

发明人： Kuo-Tung Chang ,  Wei Zheng

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G11C16/04 ,  G11C16/3468 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

摘要： A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector.

摘要翻译： 如本文所述的热孔擦除操作可以用于具有存储器单元阵列的闪存器件。 擦除操作采用自适应擦除偏置电压方案，其中响应于与初步擦除操作相对应的擦除脉冲计数来动态地调节漏极偏置电压（和/或栅极偏置电压），在该擦除脉冲计数期间相对较小部分的扇区是 擦除 以这种方式调整擦除偏置电压使得能够使用更适合于扇区的当前擦除特性的擦除偏置电压来擦除扇区的其余部分。

公开(公告)号：US20080096357A1

公开(公告)日：2008-04-24

申请号：US11551535

申请日：2006-10-20

申请人： Youseok Suh ,  Hidehiko Shiraiwa ,  Allison Holbrook ,  Angela Hui ,  Kuo-Tung Chang

发明人： Youseok Suh ,  Hidehiko Shiraiwa ,  Allison Holbrook ,  Angela Hui ,  Kuo-Tung Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material is formed over the charge trapping structure and the isolation region. A masking structure having sidewalls is formed on the layer of semiconductor material. Spacers are formed adjacent the sidewalls and the layer of semiconductor material is etched to form one or more conductive strips having opposing sides. The one or more conductive strips are formed over the active region. A dielectric material is formed adjacent to the opposing sides of each conductive strip. The dielectric material serves as a gap-filling material. A layer of semiconductor material is formed over the one or more conductive strips.

摘要翻译： 一种用于制造存储器件的方法，其包括使用禁止存储器件之间的电荷耦合的间隙填充材料。 提供了具有有源区和隔离区的半导体材料。 在有源区上形成电荷俘获结构，在电荷俘获结构和隔离区上形成一层半导体材料。 在半导体材料层上形成具有侧壁的掩模结构。 间隔件邻近侧壁形成，并且半导体材料层被蚀刻以形成具有相对侧面的一个或多个导电条。 一个或多个导电条形成在有源区上。 在每个导电带的相对侧附近形成电介质材料。 介电材料用作间隙填充材料。 在一个或多个导电条上形成半导体材料层。

公开(公告)号：US20080084765A1

公开(公告)日：2008-04-10

申请号：US11538408

申请日：2006-10-03

申请人： Kuo-Tung Chang

发明人： Kuo-Tung Chang

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/16

摘要： A memory device is provided which includes a substrate, a common P-well isolated from the substrate, a plurality of sectors, and a common sector selection transistor configured to select one of the sectors for erasure. Each of the sectors share the same common sector select transistor, and the common P-well. The selected sector is configured to be erased by applying appropriate voltages to the selected sector.

摘要翻译： 提供了一种存储器件，其包括衬底，与衬底隔离的公共P-阱，多个扇区，以及公共扇区选择晶体管，被配置为选择擦除扇区之一。 每个扇区共享相同的公共扇区选择晶体管和普通P阱。 所选择的扇区被配置为通过向选择的扇区施加适当的电压来被擦除。

公开(公告)号：US20080083946A1

公开(公告)日：2008-04-10

申请号：US11539984

申请日：2006-10-10

申请人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

发明人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

IPC分类号： H01L29/792 ,  H01L21/8238

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11568

摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.

摘要翻译： 提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。