公开(公告)号：US20230395723A1

公开(公告)日：2023-12-07

申请号：US18236265

申请日：2023-08-21

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/78618 ,  H01L29/42384 ,  H01L27/1214 ,  G11C11/4085 ,  H01L27/127 ,  H01L27/1262 ,  H01L29/78642 ,  H01L27/1255

Abstract: Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230391805A1

公开(公告)日：2023-12-07

申请号：US18327840

申请日：2023-06-01

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey ,  Stefan Uhlenbrock ,  John A. Smythe

IPC: C07F7/30 ,  C23C16/455 ,  C23C16/18

CPC classification number: C07F7/30 ,  C23C16/45553 ,  C23C16/18 ,  H01L21/02532

Abstract: A germanium precursor comprising a chemical formula of Ge(R1NC(R3)NR2)(R4) where each of R1, R2, R3, and R4 is independently selected from the group consisting of hydrogen, an alkyl, a substituted alkyl, an alkoxide, a substituted amide, an amine, a substituted amine, and a halogen. Methods of forming the germanium precursor and a precursor composition including the germanium precursor are also disclosed.

公开(公告)号：US20220344200A1

公开(公告)日：2022-10-27

申请号：US17811285

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Ken Tokashiki ,  John A. Smythe ,  Gurtej S. Sandhu

IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/311

Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

公开(公告)号：US11476251B2

公开(公告)日：2022-10-18

申请号：US16986466

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  John A. Smythe, III ,  Si-Woo Lee ,  Gurtej S. Sandhu ,  Armin Saeedi Vahdat

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/78 ,  H01L27/11578 ,  H01L27/11597

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening. A first source/drain material, a replacement channel material having backchannel passivation, and a second source/drain material are deposited in the first horizontal opening to form the three-node access device for a memory cell among the arrays of vertically stacked memory cells.

公开(公告)号：US20220320179A1

公开(公告)日：2022-10-06

申请号：US17806674

申请日：2022-06-13

Applicant: Micron Technology, Inc.

Inventor： Witold Kula ,  Wayne I. Kinney ,  Gurtej S. Sandhu

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

公开(公告)号：US11417661B2

公开(公告)日：2022-08-16

申请号：US16805802

申请日：2020-03-01

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Matthew N. Rocklein ,  Brett W. Busch

IPC: H01L27/108 ,  H01L49/02

Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.

公开(公告)号：US20220238340A1

公开(公告)日：2022-07-28

申请号：US17653790

申请日：2022-03-07

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Marko Milojevic ,  John A. Smythe ,  Timothy A. Quick ,  Sumeet C. Pandey

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.

公开(公告)号：US11289491B1

公开(公告)日：2022-03-29

申请号：US17035819

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Gurtej S. Sandhu ,  Scott E. Sills ,  Si-Woo Lee ,  John A. Smythe, III

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

公开(公告)号：US20220077176A1

公开(公告)日：2022-03-10

申请号：US17013047

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC: H01L27/11582

Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US11270909B2

公开(公告)日：2022-03-08

申请号：US16773636

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Marko Milojevic ,  John A. Smythe ,  Timothy A. Quick ,  Sumeet C. Pandey

IPC: H01L21/768 ,  H01L21/67 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.