公开(公告)号：US06858515B2

公开(公告)日：2005-02-22

申请号：US10638485

申请日：2003-08-12

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76232 ,  H01L29/0657

摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

摘要翻译： 在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷 氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

公开(公告)号：US06720234B2

公开(公告)日：2004-04-13

申请号：US10366423

申请日：2003-02-14

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

摘要翻译： 通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。 此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便 具有凸形圆形的截面形状。

公开(公告)号：US06635945B1

公开(公告)日：2003-10-21

申请号：US09580953

申请日：2000-05-30

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

IPC分类号： H01L2900

CPC分类号： H01L21/76232 ,  H01L29/0657

摘要： A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

摘要翻译： 描述半导体器件和形成器件的工艺。 该工艺包括在半导体衬底的电路形成侧上形成衬垫氧化膜; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化防止膜和焊盘氧化膜，从而暴露半导体衬底的表面; 使衬垫氧化膜水平地凹陷; 通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 以及氧化在半导体衬底中形成的沟槽。 所制造的器件具有圆形的上沟槽边缘，其通过对半导体衬底的暴露表面进行各向同性蚀刻并在沟槽氧化之前水平凹陷焊盘氧化膜而获得，由此仅需要一个氧化步骤。

公开(公告)号：US06559027B2

公开(公告)日：2003-05-06

申请号：US09845338

申请日：2001-05-01

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种半导体器件，其具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤，通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生 从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。

公开(公告)号：US06559006B2

公开(公告)日：2003-05-06

申请号：US10157978

申请日：2002-05-31

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质 介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

公开(公告)号：US06436753B1

公开(公告)日：2002-08-20

申请号：US09372007

申请日：1999-08-11

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218244

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth， 引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

公开(公告)号：US06326255B1

公开(公告)日：2001-12-04

申请号：US09675053

申请日：2000-09-29

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

IPC分类号： H01L2126

CPC分类号： H01L21/76224 ,  Y10S438/978

摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压 氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。

公开(公告)号：US06284625B1

公开(公告)日：2001-09-04

申请号：US09434308

申请日：1999-11-05

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S438/978

摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压 氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。

公开(公告)号：US06187100B1

公开(公告)日：2001-02-13

申请号：US09413890

申请日：1999-10-07

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： C23C1600

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

摘要翻译： 包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向 或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

公开(公告)号：US5444012A

公开(公告)日：1995-08-22

申请号：US278073

申请日：1994-07-20

申请人： Keiichi Yoshizumi ,  Kazushi Fukuda ,  Seiichi Ariga ,  Shuji Ikeda ,  Makoto Saeki ,  Kiyoshi Nagai ,  Soichiro Hashiba ,  Shinji Nishihara ,  Fumiyuki Kanai

发明人： Keiichi Yoshizumi ,  Kazushi Fukuda ,  Seiichi Ariga ,  Shuji Ikeda ,  Makoto Saeki ,  Kiyoshi Nagai ,  Soichiro Hashiba ,  Shinji Nishihara ,  Fumiyuki Kanai

IPC分类号： H01L21/66 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8244 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.

摘要翻译： 在将构成最终钝化膜的一部分的氧化硅膜沉积到形成在层间绝缘膜上的接合焊盘上的情况下，将氧化硅沉积步骤分成两个阶段，在第一次沉积之后，通过蚀刻将接合焊盘一次曝光 ，然后进行第二沉积，由此形成在层间绝缘膜下面的熔丝元件上形成两级沉积的氧化硅膜，而在焊盘上仅形成沉积在第二层中的氧化硅膜 阶段。 结果，在蚀刻聚酰亚胺树脂，氮化硅膜和氧化硅膜时，连续地露出接合焊盘，在同时形成的孔的底部和熔丝之间保持足够的绝缘膜厚度 元件。 此后，在将探针施加到接合焊盘的同时进行电气测试，并且如果需要，则切割位于孔下方的熔丝元件。