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公开(公告)号：US08736071B2
公开(公告)日：2014-05-27
申请号：US13285073
申请日：2011-10-31
IPC分类号： H01L23/48
CPC分类号： G06F13/4027 , G06F17/5077 , H01L23/5221 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.
摘要翻译： 半导体器件包括导电总线和导电桥。 相应的导电桥与至少一个导电总线的至少两个部分导电耦合。 当以下情况下，至少N + 1个（N + 1）通孔耦合在每个导电桥和集成电路中的相应特征之间：（1）相应导电桥的宽度小于每个导体桥的宽度 所述至少一个导电总线的至少一个导体总线的至少两个部分相互连接，并且（2）沿相应导电桥和至少一个通孔的距离小于临界距离。 N是在相应的一个导电桥和至少一个导电总线之间的多个导电耦合。
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公开(公告)号：US08658497B2
公开(公告)日：2014-02-25
申请号：US13343331
申请日：2012-01-04
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在高k电介质上，如逻辑晶体管的金属逻辑门。 在形成NVM单元的金属选择栅极的同时形成逻辑晶体管，包括形成源极/漏极。 逻辑晶体管被保护，同时形成NVM单元，包括在金属选择栅极的一部分和衬底上的电荷存储区域的一部分上使用金属纳米晶体和金属控制栅极形成电荷存储区域。 蚀刻电荷存储区域以与金属控制栅极对准。
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公开(公告)号：US08640072B1
公开(公告)日：2014-01-28
申请号：US13562538
申请日：2012-07-31
IPC分类号： G06F17/50 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76877 , G06F17/5077 , H01L21/4763 , H01L21/76816 , H01L23/5226 , H01L29/401 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.
摘要翻译： 一种方法包括在第一金属层和第二金属层之间形成连接。 第二金属层在第一金属层之上。 识别用于第一金属层和第二金属层之间的第一通孔的通孔位置。 确定第一个额外通孔的附加位置。 第一个额外的通孔被确定为压力迁移问题所必需的。 确定第二个额外通孔所需的附加位置。 第二个额外的通孔被确定为电迁移问题所必需的。 第一个通路和一个组（i）第一个额外的通孔和第二个额外的通孔（ii）第一个额外的通孔加上一些足够电迁移问题的通孔，考虑到第一个额外的通孔， 考虑到压力迁移问题，仍然有效通过数字大于零。
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公开(公告)号：US20140001432A1
公开(公告)日：2014-01-02
申请号：US13539070
申请日：2012-06-29
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
CPC分类号： H01L29/0676 , B60C23/00 , B81B1/00 , B81B2203/0361 , B82Y20/00 , B82Y30/00 , B82Y40/00 , G01L9/06 , G01N33/0031 , G02B6/107 , G02B6/126 , G02B2006/12097 , H01L21/3086 , H01L29/0665 , H01L29/66 , H01L33/18 , H01L41/1132 , H01L43/02
摘要： A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.
摘要翻译： 公开的制造混合纳米柱装置的方法包括在基底上形成掩模和硬掩模上的纳米团簇层。 然后蚀刻硬掩模以将由第一层纳米团簇形成的图案转移到硬掩模的第一区域中。 在基板上形成第二纳米团簇层。 蚀刻覆盖衬底的第二区域的硬掩模的第二区域，以在硬掩模中产生第二图案。 然后将衬底通过硬掩模蚀刻以在衬底的第一区域中形成第一组纳米柱，并在衬底的第二区域中形成第二组纳米柱。 通过改变第一和第二层纳米团簇之间的纳米团簇沉积步骤，第一组和第二组纳米颗粒将呈现不同的特征。
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115.发明申请INTEGRATING FORMATION OF A REPLACEMENT GATE TRANSISTOR AND A NON-VOLATILE MEMORY CELL USING A HIGH-K DIELECTRIC 有权使用高K电介质形成替代栅极晶体管和非易失性存储器单元公开(公告)号：US20130330893A1
公开(公告)日：2013-12-12
申请号：US13491771
申请日：2012-06-08
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L27/11534 , H01L27/11539 , H01L27/11573 , H01L29/66545 , H01L29/66833
摘要： A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate.
摘要翻译： 在NVM区域和逻辑区域中形成第一介电层。 电荷存储层形成在第一电介质层之上，并被图案化以在逻辑区域中形成伪栅极，并在NVM区域中形成电荷存储结构。 在NVM和围绕电荷存储结构和虚拟栅极的逻辑区域中形成第二介质层。 从NVM区域去除第二介电层，同时保护逻辑区域中的第二介质层。 去除虚拟门，导致开口。 在电荷存储结构之上和开口内形成第三电介质层，并且栅极层形成在第三介电层之上和开口内，其中栅极层在NVM区域内形成控制栅极层，在栅极层内形成栅极层 开幕式构成逻辑门。
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116.发明申请TECHNIQUES FOR CHECKING COMPUTER-AIDED DESIGN LAYERS OF A DEVICE TO REDUCE THE OCCURRENCE OF MISSING DECK RULES 有权检查设备的计算机辅助设计层的技术，以减少错误的规则规则的发生公开(公告)号：US20130326446A1
公开(公告)日：2013-12-05
申请号：US13484022
申请日：2012-05-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed.
摘要翻译： 用于集成电路设计的计算机辅助设计层检查的技术包括生成设备（例如，参数化单元）的表示。 计算机辅助设计（CAD）层从参数化的单元中顺序地移除，并且确定是否由相关联的卡座检测到或错过预期的错误。 然后修改相关甲板以检测错过的预期错误。
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117.发明授权Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric 有权使用层间电介质来整合替换栅晶体管和非易失性存储单元的形成公开(公告)号：US08574987B1
公开(公告)日：2013-11-05
申请号：US13491760
申请日：2012-06-08
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/823456 , H01L27/11534 , H01L29/66545
摘要： A first dielectric layer is formed over a semiconductor layer in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer in the NVM and logic regions. The charge storage layer is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed over the semiconductor layer in the NVM and logic regions which surrounds the charge storage structure and the dummy gate. The dummy gate is replaced with a logic gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. A third dielectric layer is formed over the charge storage structure, and a control gate layer is formed over the third dielectric layer.
摘要翻译： 在NVM区域和逻辑区域中的半导体层上形成第一介电层。 在NVM和逻辑区域中的第一介电层上形成电荷存储层。 对电荷存储层进行图案化以在逻辑区域中形成伪栅极，并在NVM区域中形成电荷存储结构。 在NVM的半导体层上形成第二电介质层，围绕电荷存储结构和虚拟栅极的逻辑区域形成。 虚拟门被一个逻辑门代替。 从NVM区域去除第二介电层，同时保护逻辑区域中的第二介质层。 在电荷存储结构上形成第三电介质层，并且在第三介电层上形成控制栅层。
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公开(公告)号：US20130267072A1
公开(公告)日：2013-10-10
申请号：US13780591
申请日：2013-02-28
IPC分类号： H01L21/82
CPC分类号： H01L21/82 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.
摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。
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公开(公告)号：US20130178027A1
公开(公告)日：2013-07-11
申请号：US13780574
申请日：2013-02-28
IPC分类号： H01L29/66
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/42348 , H01L29/4933 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66833 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。 在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。 保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。
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公开(公告)号：US20130105986A1
公开(公告)日：2013-05-02
申请号：US13285073
申请日：2011-10-31
CPC分类号： G06F13/4027 , G06F17/5077 , H01L23/5221 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.
摘要翻译： 半导体器件包括导电总线和导电桥。 相应的导电桥与至少一个导电总线的至少两个部分导电耦合。 当以下情况下，至少N + 1个（N + 1）通孔耦合在每个导电桥和集成电路中的相应特征之间：（1）相应导电桥的宽度小于每个导体桥的宽度 所述至少一个导电总线的至少一个导体总线的至少两个部分相互连接，并且（2）沿相应导电桥和至少一个通孔的距离小于临界距离。 N是在相应的一个导电桥和至少一个导电总线之间的多个导电耦合。
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