公开(公告)号：US20150053475A1

公开(公告)日：2015-02-26

申请号：US14463489

申请日：2014-08-19

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jung Keun Kim

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/09836 ,  H05K2201/09854

Abstract: There is provided a multi layered printed circuit board. The multi layered printed circuit board according to an exemplary embodiment of the present disclosure includes: a plurality of circuit layers; insulating layers each formed between the plurality of circuit layers; and a via penetrating through the insulating layers and the circuit layers and electrically connecting the plurality of circuit layers to each other, wherein the via includes a first via and a second via, and the second via is a large diameter via having a diameter larger than that of the first via.

Abstract translation: 提供了多层印刷电路板。 根据本公开的示例性实施例的多层印刷电路板包括：多个电路层; 绝缘层各自形成在所述多个电路层之间; 以及穿过绝缘层和电路层并且将多个电路层彼此电连接的通孔，其中所述通孔包括第一通孔和第二通孔，并且所述第二通孔是大直径通孔，其直径大于 那第一个通过。

公开(公告)号：US08536464B2

公开(公告)日：2013-09-17

申请号：US12994774

申请日：2008-05-26

Applicant: Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

Inventor： Taras Kushta ,  Jun Sakai ,  Hikaru Kouta

IPC: H05K1/11

CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

Abstract translation: 多层基板设置有布置有多个导体平面的导体平面区域; 与所述导体平面区域相邻设置的间隙区域，以使所述多个导体平面从所述间隙区域排除。 多个信号通孔设置穿过间隙区域，使得多个信号通孔与多个导体平面隔离。 导体柱连接到多个导体平面中的一个并且设置在间隙区域中的两个信号通孔之间。

公开(公告)号：US08476537B2

公开(公告)日：2013-07-02

申请号：US12675678

申请日：2007-08-31

Applicant: Taras Kushta

Inventor： Taras Kushta

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09781

Abstract: A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.

Abstract translation: 多层基板包括通过多层转换连接的平面传输线结构和信号通孔。 多层转换包括经配置以用于信号通孔和平面传输线的全值连接的信号通孔; 以及连接到信号通孔的虚拟焊盘，形成在布置在信号通孔的信号端子和平面传输线之间并与导体层隔离的导体层中的间隙孔的区域中。

公开(公告)号：US08304667B2

公开(公告)日：2012-11-06

申请号：US12920426

申请日：2009-03-24

Applicant: Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

Inventor： Takashi Yoshinaga ,  Kenji Kataoka ,  Michihito Otsuki

IPC: H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayer printed circuit board, including: a signal interconnection which transmits and receives an electrical signal between electronic components; a ground interconnection connected to a ground of a circuit; a power interconnection connected to a power layer to supply power to electronic components; at least one ground layer installed in an inner layer; at least one clearance which passes through the ground layer; and a ground via which connects the ground interconnection with the ground layer. The signal interconnection and the ground interconnection or the signal interconnection and the power interconnection are installed in a pair, and a pair of interconnection vias for interlayer connection are inserted through the clearance installed in the ground layer so that one of the pair of interconnection vias is connected to the ground layer by the ground interconnection.

Abstract translation: 一种多层印刷电路板，包括：在电子部件之间传输和接收电信号的信号互连; 连接到电路的地的接地互连; 连接到功率层以向电子部件供电的电力互连; 至少一个地层安装在内层中; 至少一个通过地层的间隙; 以及将接地互连与接地层连接的接地。 信号互连和接地互连，信号互连和电源互连成对安装，并且用于层间连接的一对互连通孔穿过安装在接地层中的间隙插入，使得一对互连通孔中的一个 通过地面互连连接到地层。

公开(公告)号：US08253031B2

公开(公告)日：2012-08-28

申请号：US12633653

申请日：2009-12-08

Applicant: Yung-Chieh Chen ,  Cheng-Hsien Lee ,  Shou-Kuo Hsu ,  Shen-Chun Li ,  Hsien-Chuan Liang ,  Shin-Ting Yen

Inventor： Yung-Chieh Chen ,  Cheng-Hsien Lee ,  Shou-Kuo Hsu ,  Shen-Chun Li ,  Hsien-Chuan Liang ,  Shin-Ting Yen

IPC: H05K1/11

CPC classification number: H05K1/0295 ,  H05K1/0239 ,  H05K1/0245 ,  H05K1/029 ,  H05K3/222 ,  H05K2201/09481 ,  H05K2201/09636 ,  H05K2201/10015 ,  H05K2201/10189 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A printed circuit board can support different connectors by selectively setting connection components on the printed circuit board without changing wiring of transmission lines or making new vias in the printed circuit board.

Abstract translation: 印刷电路板可以通过选择性地设置印刷电路板上的连接部件来支持不同的连接器，而不改变传输线的接线或在印刷电路板中形成新的通孔。

公开(公告)号：US08203082B2

公开(公告)日：2012-06-19

申请号：US12272797

申请日：2008-11-18

Applicant: Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu ,  Ying-Tso Lai

Inventor： Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu ,  Ying-Tso Lai

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09636

Abstract: A printed circuit board includes a first layout layer, a second layout layer, a copper foil layer, a first via and a second via. The first layout layer has a first signal line and a second signal line, each of which has a curved first portion. The second layout layer has a third signal line and a fourth signal line, each of which also has a curved first portion. The curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line are coupled to the first via and the second via. In this case, the curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line cooperatively generate spiral inductance characteristic.

Abstract translation: 印刷电路板包括第一布局层，第二布局层，铜箔层，第一通孔和第二通孔。 第一布局层具有第一信号线和第二信号线，每条信号线都具有弯曲的第一部分。 第二布局层具有第三信号线和第四信号线，每条信号线还具有弯曲的第一部分。 第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分耦合到第一通孔和第二通孔。 在这种情况下，第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分协同地产生螺旋电感特性。

公开(公告)号：US20110279195A1

公开(公告)日：2011-11-17

申请号：US13187910

申请日：2011-07-21

Applicant: Taras KUSHTA ,  Kaoru NARITA ,  Tomoyuki KANEKO ,  Shin-ichi OGOU

Inventor： Taras KUSHTA ,  Kaoru NARITA ,  Tomoyuki KANEKO ,  Shin-ichi OGOU

IPC: H01P5/12

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; the length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者根据通过三维全波模拟获得的数字图，定义为在时域中提供极小的超额感抗 。

公开(公告)号：US08013685B2

公开(公告)日：2011-09-06

申请号：US12281460

申请日：2007-03-02

Applicant: Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

Inventor： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

IPC: H03H7/38

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者定义为根据通过三维全波模拟获得的数值图在时域中提供最小的额外的电抗 。

公开(公告)号：US20110203843A1

公开(公告)日：2011-08-25

申请号：US12442238

申请日：2007-10-11

Applicant: Taras Kushta

Inventor： Taras Kushta

IPC: H05K9/00 ,  H05K1/11 ,  G06F17/50

CPC classification number: H05K1/0219 ,  H05K1/0237 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: To provide more compact dimensions of a via structure formed by signal via pairs and ground vias in multilayer substrate. A multilayer substrate is provided such that the multilayer substrate comprising a high-isolated via cell wherein the high-isolated via cell comprises: two signal via pairs; a shield structure around two signal via pairs consisting of ground vias and ground strips connected to ground vias wherein the shield structure is formed symmetrically in respect to two via pairs to reduce the transformation between mixed modes and also leakage from two signal via pairs; a clearance hole separating signal via pairs from other conductive parts of the multilayer substrate and having predetermined dimensions to provide broadband operation of the high-isolated via cell; and the separating strip disposed symmetrically between said signal via pairs to provide crosstalk reduction between two signal via pairs and common mode decrease.

Abstract translation: 为了提供由多层衬底中的信号通孔对和接地孔形成的通孔结构的更紧凑的尺寸。 提供多层基板，使得包括高隔离通孔单元的多层基板，其中高隔离通孔单元包括：两个信号通孔对; 围绕由连接到接地通孔的接地通孔和接地条构成的两个信号通孔对的屏蔽结构，其中屏蔽结构相对于两个通孔对对称地形成，以减少混合模式之间的变换以及来自两个信号通孔对的泄漏; 隔离孔将信号经由对与多层基板的其它导电部分分离并具有预定尺寸以提供高隔离通孔单元的宽带操作; 并且分离带对称地布置在所述信号通孔对之间，以提供两个信号通孔对之间的串扰减小和共模减少。

公开(公告)号：US07968802B2

公开(公告)日：2011-06-28

申请号：US11967017

申请日：2007-12-29

Applicant: Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu

Inventor： Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu

IPC: H05K1/11 ,  H01P1/00

CPC classification number: H05K1/0245 ,  H05K1/0228 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/09636 ,  H05K2201/097

Abstract: A printed circuit board (PCB) includes a differential pair having a first differential trace and a second differential trace, a first via having an upper cap and a lower cap, and a second via having an upper cap and a lower cap. The first differential trace includes a first segment and a second segment, the second differential trace includes a third segment and a fourth segment. The first and the third segments are electrically coupled to the upper caps of the first and the second vias respectively. The second and the fourth segments are electrically coupled to the lower caps of the first and the second vias respectively. The first and the third segments extend from corresponding upper caps in different directions, the second and the fourth segments extend from corresponding lower caps in different directions.

Abstract translation: 印刷电路板（PCB）包括具有第一差分迹线和第二差分迹线的差分对，具有上盖和下盖的第一通孔以及具有上盖和下盖的第二通孔。 第一差分迹线包括第一段和第二段，第二差分迹线包括第三段和第四段。 第一和第三段分别电耦合到第一和第二通孔的上盖。 第二和第四段分别电耦合到第一和第二通孔的下盖。 第一和第三段从相应的上盖在不同的方向上延伸，第二和第四段从相应的下盖在不同的方向延伸。