公开(公告)号：US07841505B2

公开(公告)日：2010-11-30

申请号：US12320964

申请日：2009-02-10

Applicant: Sung-Soo Lee ,  Ki-Taik Oh ,  Jung-Hyeon Kim

Inventor： Sung-Soo Lee ,  Ki-Taik Oh ,  Jung-Hyeon Kim

IPC: B23K37/00

CPC classification number: H01L24/85 ,  B23K20/007 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/78301 ,  H01L2224/786 ,  H01L2224/851 ,  H01L2224/85205 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wire clamp includes a pair of clamp arms at a predetermined distance from each other to define an interval therebetween for a bonding wire, a clamp body coupled to the clamp arms, the clamp body configured to adjust the predetermined distance between the clamp arms with respect to a process to be performed, a clamping section in each clamp arm, the clamping section having concave portions facing the interval between the clamp arms, the concave portions being configured to contact the bonding wire when the clamp arms are brought close together, and at least one abrasion prevention member in each clamping section, the abrasion prevention members being configured to prevent abrasion during contact with the bonding wire.

Abstract translation: 电线夹具包括彼此隔开预定距离的一对夹持臂，以在其间限定用于接合线的间隔，联接到夹紧臂的夹具本体，夹具主体被配置为相对于夹具臂之间的预定距离调整 对于要执行的处理，每个夹持臂中的夹持部分，夹持部分具有面对夹紧臂之间的间隔的凹部，凹部被构造成在夹紧臂靠近在一起时与接合线接触，并且在 每个夹紧部分中的至少一个防磨损构件，所述防磨构件被构造成防止在与所述接合线接触期间的磨损。

公开(公告)号：US07816677B2

公开(公告)日：2010-10-19

申请号：US12112292

申请日：2008-04-30

Applicant: Sung-Soo Lee ,  Jin-Koo Chung ,  Seong-Min Kim ,  Chang-Woong Chu

Inventor： Sung-Soo Lee ,  Jin-Koo Chung ,  Seong-Min Kim ,  Chang-Woong Chu

IPC: H01L35/24 ,  H01L51/00

CPC classification number: H01L51/5265 ,  H01L27/3213 ,  H01L27/322 ,  H01L27/3244 ,  H01L27/3258 ,  H01L51/5215

Abstract: An organic light emitting device includes first, second, and third pixels each displaying a different color. Each pixel includes a first electrode, a second electrode facing the first electrode, and an emission layer between the first and second electrodes. The first electrodes of the first and second pixels respectively include a first transparent conductive layer and a translucent conductive layer disposed on at least one of lower and upper portions of the first transparent conductive layer and forming microcavities together with the second electrodes, and the first electrode of the third pixel includes a second transparent conductive layer that is different from the first transparent conductive layer and a translucent conductive layer disposed on at least one of upper and lower portions of the second transparent conductive layer and forming a microcavity together with the second electrode.

Abstract translation: 有机发光器件包括每个显示不同颜色的第一，第二和第三像素。 每个像素包括第一电极，面对第一电极的第二电极和第一和第二电极之间的发射层。 第一和第二像素的第一电极分别包括第一透明导电层和设置在第一透明导电层的下部和上部中的至少一个上的半透明导电层，并与第二电极一起形成微腔，并且第一电极 所述第三像素包括与所述第一透明导电层不同的第二透明导电层和设置在所述第二透明导电层的上部和下部中的至少一个上的透光性导电层，并与所述第二电极一起形成微腔。

公开(公告)号：US07812523B2

公开(公告)日：2010-10-12

申请号：US11560153

申请日：2006-11-15

Applicant: Jae-hoon Jung ,  Sung-soo Lee ,  Ji-hye Choi

Inventor： Jae-hoon Jung ,  Sung-soo Lee ,  Ji-hye Choi

IPC: H01L51/50 ,  G09G3/10

CPC classification number: H01L51/5203 ,  H01L27/322 ,  H01L27/3276 ,  H01L51/5284 ,  H01L2251/5315

Abstract: A display device includes a thin film transistor formed on a first insulating substrate, a first electrode electrically connected with the thin film transistor, an emission layer formed on the first electrode, a second electrode formed on the emission layer, an auxiliary electrode shaped like a mesh to at least partially expose the first electrode, the auxiliary electrode being electrically connected with the second electrode and receiving a common voltage therefrom, and a second insulating substrate placed on the auxiliary electrode. The exemplary embodiments of a display device, and a method of manufacturing the same, according to the present invention can apply a common voltage efficiently throughout the display and have an improved contrast ratio.

Abstract translation: 显示装置包括形成在第一绝缘基板上的薄膜晶体管，与薄膜晶体管电连接的第一电极，形成在第一电极上的发射层，形成在发射层上的第二电极，形状类似于 筛网以至少部分地暴露第一电极，辅助电极与第二电极电连接并从其接收公共电压，以及放置在辅助电极上的第二绝缘基板。 根据本发明的显示装置的示例性实施例及其制造方法可以在整个显示器上有效地施加公共电压并且具有改善的对比度。

公开(公告)号：US07724575B2

公开(公告)日：2010-05-25

申请号：US12035028

申请日：2008-02-21

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: In one aspect a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

Abstract translation: 在一个方面，提供可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。

公开(公告)号：US20090200922A1

公开(公告)日：2009-08-13

申请号：US12121188

申请日：2008-05-15

Applicant: Sung-Soo LEE ,  Jun-Ho CHOI ,  Chang-Woong CHU ,  Seong-Min KIM

Inventor： Sung-Soo LEE ,  Jun-Ho CHOI ,  Chang-Woong CHU ,  Seong-Min KIM

IPC: H01L27/32 ,  H01J9/02

CPC classification number: H01L51/5265 ,  H01L27/3206 ,  H01L27/3213 ,  H01L27/322 ,  H01L51/5036 ,  H01L51/5215 ,  H01L2251/308 ,  H01L2251/558

Abstract: A method for manufacturing an organic light emitting diode (“OLED”) display which includes first and second pixels each displaying a different color, the method includes: sequentially depositing a first transparent conductive layer and a translucent conductive layer; forming an intermediate first electrode on the second pixel by photolithography and etching of the translucent conductive layer; depositing a second transparent conductive layer on the intermediate first electrode and the first transparent conductive layer; forming a first electrode of the first pixel which includes upper and lower layers on the first pixel and a first electrode of the second pixel which includes a lower first electrode, an intermediate first electrode, and an upper first electrode by photolithography and etching of the second transparent conductive layer and the first transparent conductive layer; forming an emission layer on the first electrodes of the first and second pixels; and forming a second electrode on the emission layer.

Abstract translation: 一种制造有机发光二极管（“OLED”）显示器的方法，其包括每个显示不同颜色的第一和第二像素，所述方法包括：顺序地沉积第一透明导电层和半透明导电层; 通过光刻和半透明导电层的蚀刻在第二像素上形成中间第一电极; 在所述中间第一电极和所述第一透明导电层上沉积第二透明导电层; 形成第一像素的第一电极，其包括第一像素上的上层和下层，以及第二像素的第一电极，其包括下第一电极，中间第一电极和上第一电极，通过光刻和第二像素的蚀刻 透明导电层和第一透明导电层; 在第一和第二像素的第一电极上形成发射层; 以及在所述发射层上形成第二电极。

公开(公告)号：US20090097314A1

公开(公告)日：2009-04-16

申请号：US12333344

申请日：2008-12-12

Applicant: Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

Inventor： Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

IPC: G11C16/02 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

Abstract translation: 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US07480177B2

公开(公告)日：2009-01-20

申请号：US11870528

申请日：2007-10-11

Applicant: Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

Inventor： Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

Abstract translation: 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US20080206567A1

公开(公告)日：2008-08-28

申请号：US11794634

申请日：2005-12-28

Applicant: Byung Hoon Min ,  Kyung Heum Kim ,  Seung Bum Kim ,  Sung Soo Lee ,  Kyoung Bae Park ,  Nam Gyol Kim ,  Byoung Jae Yoo

Inventor： Byung Hoon Min ,  Kyung Heum Kim ,  Seung Bum Kim ,  Sung Soo Lee ,  Kyoung Bae Park ,  Nam Gyol Kim ,  Byoung Jae Yoo

IPC: B05D5/12 ,  B32B15/02 ,  B32B37/02 ,  C25D5/00 ,  C25D3/12 ,  B32B37/24

CPC classification number: H01B1/02 ,  C23C18/1635 ,  C23C18/1641 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/285 ,  C23C18/30 ,  C23C18/36 ,  C23C18/405 ,  C23C28/00 ,  C23C28/021 ,  C23C28/023 ,  C25D3/60 ,  C25D7/00 ,  C25D17/20 ,  H01L23/49816 ,  H01L24/01 ,  H01L24/80 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/2989 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/0221 ,  Y02P70/613 ,  Y10T428/2991 ,  Y10T428/2993 ,  H01L2924/00

Abstract: Plastic conductive particles having an outer diameter of 2.5 μm˜1 mm obtained by sequentially plating a 0.1˜10 μm thick metal plating layer and a 1˜100 μm thick Pb solder layer or a Pb-free solder layer on plastic core beads having a high elastic modulus of compression, and a method of manufacturing thereof. The method of manufacturing the plastic conductive particles includes preparing plastic core beads having excellent thermal properties and a high elastic modulus of compression, etching surfaces of the plastic core beads for surface treatment thereof, forming a metal plating layer via electroless plating to improve adhesion between the bead surface and the metal plating layer, and then forming a solder layer such that a sealed hexagonal barrel is immersed in an electroplating solution and then an electroplating process is conducted using a mesh barrel rotating 360° at 6˜10 rpm or a mesh barrel having a structure in which one surface of a conventional sealed hexagonal barrel is open, and rotating 200° in right and left directions at 1˜5 rpm, to manufacture plastic conductive particles having a size of 1 mm or less. The plastic conductive particles of this invention enable the maintenance of packaging gaps, and thus can be applied to IC packaging, LCD packaging and other conductive materials.

Abstract translation: 通过在具有高的塑料芯珠上顺序镀覆0.1〜10μm厚的金属镀层和1〜100μm厚的Pb焊料层或无铅焊料层，得到外径为2.5μm〜1mm的塑料导电性颗粒 弹性模量，及其制造方法。 制造塑料导电颗粒的方法包括制备具有优异的热性能和高弹性模量的塑性芯珠，用于表面处理的塑料芯珠的蚀刻表面，通过无电镀形成金属镀层，以改善 珠表面和金属镀层，然后形成焊接层，使得将密封的六边形圆筒浸入电镀溶液中，然后使用以6〜10rpm旋转360°的网筒进行电镀工艺，或者具有 常规密封六角筒的一个表面打开并以1〜5rpm左右旋转200度左右的结构，制造尺寸为1mm以下的塑料导电性粒子。 本发明的塑料导电颗粒能够保持包装间隙，因此可以应用于IC封装，LCD封装和其他导电材料。

公开(公告)号：US20080168214A1

公开(公告)日：2008-07-10

申请号：US11969261

申请日：2008-01-04

Applicant: Oh-Suk Kwon ,  Sung-Soo Lee ,  Dae-Seok Byeon

Inventor： Oh-Suk Kwon ,  Sung-Soo Lee ,  Dae-Seok Byeon

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F12/0246 ,  G06F2212/2022

Abstract: A memory system and a method of provided scrambled address data are disclosed. The method includes converting external address data into row and column addresses provided to a flash memory device, and designating certain scrambled address data values within the external address data and ignoring a current data access operation associated with external address data including a scrambled address data value, such that the plurality of physical pages in each memory block is not selected by the internal address data.

Abstract translation: 公开了一种提供加扰地址数据的存储系统和方法。 该方法包括将外部地址数据转换成提供给闪存设备的行和列地址，以及指定外部地址数据内的某些加扰地址数据值，并忽略与包括加扰地址数据值的外部地址数据相关联的当前数据访问操作， 使得每个存储器块中的多个物理页不被内部地址数据选择。

公开(公告)号：US20080042946A1

公开(公告)日：2008-02-21

申请号：US11841106

申请日：2007-08-20

Applicant: Kyong-Tae Park ,  Beohm-Rock Choi ,  Young-Soo Yun ,  Sung-Soo Lee ,  Young-Rok Song ,  Ji-Hye Choi

Inventor： Kyong-Tae Park ,  Beohm-Rock Choi ,  Young-Soo Yun ,  Sung-Soo Lee ,  Young-Rok Song ,  Ji-Hye Choi

IPC: G09G3/32

CPC classification number: G09G3/3275 ,  G09G2300/0439 ,  G09G2300/0842 ,  G09G2310/0235 ,  G09G2310/027

Abstract: A display panel includes a plurality of data lines each extended in a first direction substantially parallel with each other, a plurality of driving voltage lines each extended substantially parallel with the plurality of data lines, a plurality of gate lines each extended in a second direction substantially perpendicular to the first direction and a plurality of unit pixels each including a plurality of sub-pixels, each sub-pixel of a corresponding unit pixel having two short sides defined by two adjacent data lines and two long sides defined by two adjacent gate lines. Each sub-pixel of the corresponding unit pixel includes a switching element electrically connected to a same data line of the two adjacent data lines and one of the two adjacent gate lines, and a driving element electrically connected to the switching element and a same driving voltage line, the driving element drives a light-emitting element.

Abstract translation: 显示面板包括多个数据线，每条数据线在彼此大致平行的第一方向上延伸;多条驱动电压线，每条驱动电压线基本上与多条数据线平行;多条栅极线，分别沿第二方向延伸 垂直于第一方向的多个单位像素和包括多个子像素的多个单位像素，相应单位像素的每个子像素具有由两个相邻数据线限定的两个短边和由两个相邻栅极线限定的两个长边。 对应的单位像素的每个子像素包括电连接到两个相邻数据线的相同数据线和两个相邻栅极线中的一个的开关元件，以及电连接到开关元件的驱动元件和相同的驱动电压 驱动元件驱动发光元件。