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    MULTILAYER HOSE WITH LEAK PREVENTATIVE INTERFACIAL LAYER CONTAINING SUPER ABSORBENT POLYMER (SAP)
    123.
    发明申请
    MULTILAYER HOSE WITH LEAK PREVENTATIVE INTERFACIAL LAYER CONTAINING SUPER ABSORBENT POLYMER (SAP) 有权
    多层软管与含有超吸收聚合物（SAP）的泄漏预处理界面层

    公开(公告)号：US20140076524A1

    公开(公告)日：2014-03-20

    申请号：US13623386

    申请日：2012-09-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Dylan J. Boday ,  Joseph Kuczynski ,  Jason T. Wertz ,  Jing Zhang

    IPC: F28D15/00 ,  B65H81/00 ,  F16L11/00

    CPC classification number: F16L11/00 ,  B29C47/0023 ,  B29C47/021 ,  B29C47/04 ,  B32B1/08 ,  B32B25/08 ,  B32B25/16 ,  B32B25/20 ,  B32B27/306 ,  B32B27/308 ,  B32B27/34 ,  B32B2262/0261 ,  B32B2262/0284 ,  B32B2262/04 ,  B32B2307/726 ,  B32B2307/728 ,  B32B2307/73 ,  B32B2597/00 ,  F16L11/08 ,  F16L11/085 ,  Y10T428/139

    Abstract: A multilayer hose is provided with a leak preventative interfacial layer that includes a super absorbent polymer (SAP) interposed between an inner layer and an outer layer. In one embodiment, the inner and outer layers are made of ethylene propylene diene monomer (M-class) (EPDM) rubber, and the interfacial layer is covalently bonded to the inner layer (and, optionally, to the outer layer) via a curing reaction between the EPDM rubber of at least the inner layer and a vinyl functionalized reaction product of alginic acid and acryloyl chloride of the interfacial layer. In addition, a reinforcement layer (e.g., textile filaments braided, knitted, or spirally wound onto the interfacial layer) is disposed between the inner and outer layers. In some embodiments, one or more SAP-equipped multilayer hoses interconnect liquid-coolant cooling system components (e.g., cold plates, headers, manifolds, pumps, reservoirs, and heat exchangers) of an apparatus that removes heat from electronic components.

    Abstract translation: 多层软管设置有防漏界面层，其包括介于内层和外层之间的高吸水性聚合物（SAP）。 在一个实施方案中，内层和外层由乙烯丙烯二烯单体（M级）（EPDM）橡胶制成，并且界面层通过固化共价结合到内层（和任选地到外层） 至少内层的EPDM橡胶与界面层的海藻酸和丙烯酰氯的乙烯基官能化反应产物之间的反应。 此外，在内层和外层之间设置加强层（例如，编织，编织或螺旋缠绕在界面层上的织物细丝）。 在一些实施例中，一个或多个配备SAP的多层软管将从电子部件移除热量的装置的液体 - 冷却剂冷却系统组件（例如，冷板，集管，歧管，泵，储存器和热交换器）相互连接。

    Plated Through Hole Void Detection in Printed Circuit Boards by Detecting A pH-Sensitive Component
    124.
    发明申请
    Plated Through Hole Void Detection in Printed Circuit Boards by Detecting A pH-Sensitive Component 有权
    通过检测pH敏感元件在印刷电路板中镀覆通孔检测

    公开(公告)号：US20140076478A1

    公开(公告)日：2014-03-20

    申请号：US14088107

    申请日：2013-11-22

    Applicant: International Business Machines Corporation

    Inventor： Bruce John Chamberlin ,  Chang-Min Chu ,  Gao-Bin Hu ,  Joseph Kuczynski ,  Kaspar Ka Chung Tsang

    IPC: G01N21/80 ,  H05K3/22

    CPC classification number: G01N21/80 ,  H05K1/0269 ,  H05K3/22 ,  H05K3/225 ,  H05K3/42 ,  H05K2203/16 ,  H05K2203/161 ,  Y10T29/49004

    Abstract: An approach is provided in which a pH-indicating compound is incorporated in a printed circuit board. The printed circuit board includes a number of layers with the pH-sensitive indicator being incorporated in one of the layers. Conductive pathways are formed from a conductive sheet laminated onto an outer surface of the printed circuit board. The printed circuit board is exposed to a pH-activating solution. Plated-through hole defects in the printed circuit board are identified by detecting a color formation at a surface location of the printed circuit board that corresponds to the plated-through hole defect. Another approach is also provided where a pH-activating compound is incorporated in one of the layers of the printed circuit board which is then exposed to a pH-indicating solution to produce the color formation that identifies the location of the plated-through hole defect.

    Abstract translation: 提供了其中将pH指示化合物并入印刷电路板中的方法。 印刷电路板包括多个层，其中pH敏感指示器被结合在一个层中。 导电路径由层叠在印刷电路板的外表面上的导电片形成。 将印刷电路板暴露于pH活化溶液。 通过检测印刷电路板的与镀通孔缺陷相对应的表面位置处的颜色形成来识别印刷电路板中的通孔缺陷。 还提供另一种方法，其中将pH活化化合物并入印刷电路板的一个层中，然后暴露于pH指示溶液以产生识别电镀通孔缺陷位置的着色层。

    CIRCUIT APPARATUS HAVING A ROUNDED DIFFERENTIAL PAIR TRACE
    125.
    发明申请
    CIRCUIT APPARATUS HAVING A ROUNDED DIFFERENTIAL PAIR TRACE 审中-公开
    具有圆形差分对线追踪的电路设备

    公开(公告)号：US20130240250A1

    公开(公告)日：2013-09-19

    申请号：US13888009

    申请日：2013-05-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

    IPC: H05K1/02

    CPC classification number: H05K1/0296 ,  C25D5/022 ,  C25D5/10 ,  C25D7/00 ,  H05K1/0245 ,  H05K3/18 ,  H05K3/184 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155

    Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

    Abstract translation: 具有第一适应性掩模部分的第一艺术品层允许渐变量的光进入下面的第一光致抗蚀剂层。 在显影第一光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于产生圆形迹线的至少下部。 电介质层层叠在下部，具有第二可适应掩模部分的第二艺术品层允许渐变量的光通过第二光致抗蚀剂层。 在显影第二光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于至少形成圆形迹线的上部。 去除光致抗蚀剂和介电层，导致具有圆形差分对迹线的电路设备。

    Conductive particle interconnect switch
    126.
    发明授权
    Conductive particle interconnect switch 有权

    公开(公告)号：US12075702B2

    公开(公告)日：2024-08-27

    申请号：US17811374

    申请日：2022-07-08

    Applicant: International Business Machines Corporation

    Inventor： Matthew Doyle ,  Joseph Kuczynski ,  Patrick Egan ,  Jeffrey N. Judd ,  Timothy J. Tofil

    IPC: H01L41/04 ,  H01H1/029 ,  H01H57/00 ,  H10N30/20 ,  H10N30/857

    CPC classification number: H10N30/20 ,  H01H1/029 ,  H01H57/00 ,  H10N30/857

    Abstract: Provided is an apparatus comprising a conductive particle interconnect (CPI). The CPI includes an elastomeric carrier and a plurality of conductive particles dispersed therein. The elastomeric carrier includes an electroactive polymer (EAP) configured to move between a first position and a second position in response to an electrical field. The CPI is configured to exhibit a first electrical resistance when the EAP is in the first position and a second electrical resistance when the EAP is in the second position. The apparatus further comprises one or more electrodes electrically coupled to the CPI. The electrodes are configured to generate the electrical field within the CPI. The apparatus further comprises one or more insulators coupled to the CPI. The one or more insulators are configured to constrain expansion of the CPI in at least one direction.

    Fabricating an asymmetric printed circuit board with minimized warpage
    129.
    发明授权
    Fabricating an asymmetric printed circuit board with minimized warpage 有权

    公开(公告)号：US11523519B2

    公开(公告)日：2022-12-06

    申请号：US16239043

    申请日：2019-01-03

    Applicant: International Business Machines Corporation

    Inventor： Bruce J. Chamberlin ,  Joseph Kuczynski ,  Paula M. Nixa

    IPC: H05K3/46

    Abstract: A method for fabricating an asymmetric printed circuit board with minimized warpage. The method includes determining a first resin area and a second resin area in a stack of printed circuit board layers. The method further includes performing computer modeling to predict a warpage of the printed circuit board layers during a predicted use of the printed circuit board layers. The method further includes determining a first target coefficient of thermal expansion for the first resin area and a second target coefficient of thermal expansion for the second resin area based on the computer modeling. The method further includes differentially curing resin in the first resin area and the second resin area based on the first target coefficient of thermal expansion and the second target coefficient of thermal expansion. The method further includes forming an asymmetric printed circuit board from the stack of printed circuit board layers.

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