公开(公告)号：US07273638B2

公开(公告)日：2007-09-25

申请号：US10338254

申请日：2003-01-07

申请人： Michael Belyansky ,  Oleg Glushenkov ,  Andreas Knorr

发明人： Michael Belyansky ,  Oleg Glushenkov ,  Andreas Knorr

IPC分类号： H05H1/46 ,  B05D3/06 ,  B05D3/14 ,  C23C16/40 ,  C23C16/505 ,  H01L21/473 ,  C23C16/509

CPC分类号： H01L21/31658 ,  C23C8/36 ,  H01J37/321 ,  H01J2237/338 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662

摘要： A method of oxidizing a substrate having area of about 30,000 mm2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal suicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1e12 cm−3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

摘要翻译： 一种氧化具有约30,000mm 2以上面积的基材的方法。 该表面优选由含硅材料，例如硅，硅锗，碳化硅，氮化硅和金属硅化物组成。 通常对氧气（例如Ne，Ar，Kr，Xe和/或Rn）通常不与氧反应的含氧气体和稀释气体的混合物被电离以产生电子密度为至少约1e12cm -3，并且包含平均温度大于约1eV的环境电子。 衬底表面被能量粒子氧化，主要由等离子体中产生的原子氧组成，形成厚度基本均匀的氧化膜。 衬底的氧化在低于约700℃的温度下进行，例如在约室温，20℃和约500℃之间。

公开(公告)号：US20060258177A1

公开(公告)日：2006-11-16

申请号：US10908441

申请日：2005-05-12

申请人： Bernd Kastenmeier ,  Andreas Knorr

发明人： Bernd Kastenmeier ,  Andreas Knorr

IPC分类号： H01L21/00

CPC分类号： H01L21/67069 ,  H01L21/02046 ,  H01L21/02087 ,  H01L21/02096 ,  H01L21/3065

摘要： A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized to effectuate a cleaning of an edge portion of a wafer.

公开(公告)号：US07091103B2

公开(公告)日：2006-08-15

申请号：US10314865

申请日：2002-12-09

申请人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

发明人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

IPC分类号： H01L21/76 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/31055 ,  H01L27/1087 ,  H01L27/10894

摘要： CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

摘要翻译： 包含具有沟槽电容器的DRAM阵列的集成电路的CMP用氧化物填充沟槽，导致与周围的支撑结构中的浓度相比密集的氧化物结构的阵列，因此具有更高的负载。 保形层沉积在晶片上，增加阵列中的负载，但填充有效区域之间的空间。 覆盖蚀刻去除阵列和支撑体中的材料。 块蚀刻平衡阵列中的材料和支撑体的数量。 阵列中的补充氧化物沉积将结构之间的空间填充到几乎均匀的密度。

公开(公告)号：US06437401B1

公开(公告)日：2002-08-20

申请号：US09824957

申请日：2001-04-03

申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

IPC分类号： H01L2976

CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。

公开(公告)号：US06294423B1

公开(公告)日：2001-09-25

申请号：US09718211

申请日：2000-11-21

申请人： Rajeev Malik ,  Mihel Seitz ,  Andreas Knorr

发明人： Rajeev Malik ,  Mihel Seitz ,  Andreas Knorr

IPC分类号： H01L218242

CPC分类号： H01L21/76229 ,  H01L27/1087

摘要： A method for forming isolation trenches for a semiconductor device forms, in a substrate, a plurality of trenches having different widths including widths above a threshold size and widths below a threshold size. The plurality of trenches have a same first depth. A masking layer is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches is etched to extend the trenches with the widths above the threshold size to different depths.

摘要翻译： 用于形成用于半导体器件的隔离沟槽的方法在衬底中形成具有不同宽度的多个沟槽，所述宽度包括高于阈值尺寸的宽度和低于阈值尺寸的宽度。 多个沟槽具有相同的第一深度。 掩蔽层沉积在多个沟槽中，掩模层具有足够的厚度以使沟槽线宽度高于阈值尺寸，并以宽度低于阈值尺寸完全填充沟槽。 通过蚀刻掩模层，将衬底的一部分暴露在沟槽底部，宽度高于阈值大小。 多个沟槽被蚀刻以将具有高于阈值尺寸的宽度的沟槽延伸到不同的深度。

公开(公告)号：US08653109B2

公开(公告)日：2014-02-18

申请号：US12440423

申请日：2007-08-30

申请人： Peter Nell ,  Walter Hübsch ,  Barbara Albrecht-Küpper ,  Joerg Keldenich ,  Andreas Knorr

发明人： Peter Nell ,  Walter Hübsch ,  Barbara Albrecht-Küpper ,  Joerg Keldenich ,  Andreas Knorr

IPC分类号： A61K31/444 ,  C07D211/60

CPC分类号： C07D417/14 ,  A61K31/444 ,  A61K31/501 ,  A61K31/506 ,  A61K31/5377 ,  A61K45/06 ,  C07D213/85 ,  C07D401/14 ,  C07D409/14 ,  C07D413/14

摘要： The present invention relates to novel substituted 2,4′- and 3,4′-bipyridine derivatives, to processes for their preparation, to their use for the treatment and/or prophylaxis of diseases and to their use for preparing medicaments for the treatment and/or prophylaxis of diseases, preferably for the treatment and/or prevention of hypertension and other cardiovascular disorders.

摘要翻译： 本发明涉及新的取代的2,4'-和3,4'-联吡啶衍生物，其制备方法，其用于治疗和/或预防疾病的用途及其用于制备治疗用药物和 /或预防疾病，优选用于治疗和/或预防高血压和其它心血管疾病。

公开(公告)号：US20130187236A1

公开(公告)日：2013-07-25

申请号：US13354844

申请日：2012-01-20

申请人： Ruilong Xie ,  Xiuyu Cai ,  Robert Miller ,  Andreas Knorr

发明人： Ruilong Xie ,  Xiuyu Cai ,  Robert Miller ,  Andreas Knorr

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

摘要： Disclosed herein are methods of forming replacement gate structures. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity, forming a layer of insulating material in the gate cavity and forming a layer of metal within the gate cavity above the layer of insulating material. The method further includes forming a sacrificial material in the gate cavity so as to cover a portion of the layer of metal and thereby define an exposed portion of the layer of metal, performing an etching process on the exposed portion of the layer of metal to thereby remove the exposed portion of the layer of metal from within the gate cavity, and, after performing the etching process, removing the sacrificial material and forming a conductive material above the remaining portion of the layer of metal.

摘要翻译： 这里公开了形成替换栅极结构的方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，去除牺牲栅极结构从而限定栅极腔，在栅极腔中形成绝缘材料层并在栅极腔内形成金属层 绝缘材料层。 该方法还包括在栅腔中形成牺牲材料以覆盖金属层的一部分，从而限定金属层的暴露部分，对金属层的暴露部分进行蚀刻工艺，由此 从栅极腔内去除金属层的暴露部分，并且在执行蚀刻工艺之后，去除牺牲材料并在金属层的剩余部分上方形成导电材料。

公开(公告)号：US08361870B2

公开(公告)日：2013-01-29

申请号：US12843350

申请日：2010-07-26

申请人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

发明人： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

摘要： A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

摘要翻译： 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US20080179281A1

公开(公告)日：2008-07-31

申请号：US11872399

申请日：2007-10-15

申请人： Doug H. Lee ,  Andreas Knorr

发明人： Doug H. Lee ,  Andreas Knorr

IPC分类号： B31D3/00

CPC分类号： H01L21/0337 ,  H01L21/0274

摘要： Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.

摘要翻译： 提供了具有小特征尺寸的装置的制造方法。 在示例性实施例中，一种方法包括形成覆盖主体材料层的图案化的第一掩模层，并且各向同性地蚀刻图案化的第一掩模层。 沉积覆盖图案化的第一掩模层的第二掩模层，并暴露各向同性蚀刻的图案化的第一掩模层。 去除各向同性蚀刻的图案化的第一掩模层，并蚀刻主体材料层以在其中形成特征。

公开(公告)号：US07297636B1

公开(公告)日：2007-11-20

申请号：US11669389

申请日：2007-01-31

申请人： Doug H. Lee ,  Andreas Knorr

发明人： Doug H. Lee ,  Andreas Knorr

IPC分类号： H01L21/302

CPC分类号： H01L21/0337 ,  H01L21/0274

摘要： Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.

摘要翻译： 提供了具有小特征尺寸的装置的制造方法。 在示例性实施例中，一种方法包括形成覆盖主体材料层的图案化的第一掩模层，并且各向同性地蚀刻图案化的第一掩模层。 沉积覆盖图案化的第一掩模层的第二掩模层，并暴露各向同性蚀刻的图案化的第一掩模层。 去除各向同性蚀刻的图案化的第一掩模层，并蚀刻主体材料层以在其中形成特征。