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    Voltage generator circuit
    121.
    发明授权
    Voltage generator circuit 有权

    公开(公告)号：US09641068B2

    公开(公告)日：2017-05-02

    申请号：US14667442

    申请日：2015-03-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Toru Tanzawa

    IPC: H03K3/10 ,  H02M3/07 ,  G11C16/30 ,  H02M1/36

    CPC classification number: H02M3/07 ,  G11C16/30 ,  H02M1/36 ,  H02M3/073

    Abstract: Embodiments are provided that include a circuit for generating voltage in a memory. One such circuit includes a charge pump circuit including a first transistor, a high-voltage switch circuit, and a cut-off switch circuit arranged to reduce leakage current from the charge pump circuit. The cut-off switch circuit includes a second transistor, wherein an output of the charge pump circuit is coupled to one of a source node and a drain node of the second transistor, and a first control signal is input at a gate of the second transistor. Further embodiments provide a method for generating voltage. One such method includes enabling a first transistor coupled to an output of a charge pump circuit when the charge pump is operating and disabling the first transistor coupled to the output of the charge pump circuit when the charge pump circuit is not operating.

    Data Line Arrangement and Pillar Arrangement in Apparatuses
    124.
    发明申请
    Data Line Arrangement and Pillar Arrangement in Apparatuses 有权
    设备中的数据线布置和柱布置

    公开(公告)号：US20160268280A1

    公开(公告)日：2016-09-15

    申请号：US14656980

    申请日：2015-03-13

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: H01L27/115 ,  H01L23/528 ,  H01L29/788 ,  H01L29/792 ,  H01L29/16 ,  H01L29/04

    CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, ds; and a distance to four of the six neighboring pillars is a long distance, dl. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, ds, and a distance between neighboring pillars that are not in common rows as one another is a long distance, dl.

    Abstract translation: 一些实施例包括具有改进的六边形填充装置中的半导体柱的装置。 改进的六边形填充装置包括具有7个不同柱的至少一部分的重复图案。 7个不同柱子中的每一个立即毗邻六个相邻的支柱。 距离六个相邻柱子中的两个距离是短距离的; 距离六个相邻柱子中的四个距离是远的距离，dl。 一些实施例包括具有包装装置中的半导体柱的装置。 包装装置包括交替的第一排和第二排，第一排中的柱相对于第二排中的柱横向偏移。 彼此相邻的公共行中的相邻柱之间的距离是短距离ds，并且彼此不是共同行的相邻柱之间的距离是长距离d1。

    Memory devices having data lines included in top and bottom conductive lines
    126.
    发明授权
    Memory devices having data lines included in top and bottom conductive lines 有权
    具有包括在顶部和底部导电线中的数据线的存储器件

    公开(公告)号：US09437253B2

    公开(公告)日：2016-09-06

    申请号：US14330737

    申请日：2014-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C5/06 ,  G11C16/04 ,  H01L27/115 ,  G11C8/14

    CPC classification number: G11C5/06 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described.

    Abstract translation: 一些实施例包括具有第一组导线的设备和方法，第二组导线，以及位于设备的不同级别并被布置在存储器单元串中的存储单元。 第一组导线的至少一部分被配置为第一组数据线。 第二组导线的至少一部分被配置为第二组数据线。 每个存储器串耦合到第一组导线中的相应导线和第二组导线中的相应导线。 描述包括附加装置和方法的其他实施例。

    FIELD EFFECT TRANSISTORS HAVING A FIN
    129.
    发明申请
    FIELD EFFECT TRANSISTORS HAVING A FIN 审中-公开
    具有FIN的场效应晶体管

    公开(公告)号：US20150349126A1

    公开(公告)日：2015-12-03

    申请号：US14294266

    申请日：2014-06-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Toru Tanzawa

    IPC: H01L29/78 ,  H01L27/112 ,  H01L27/115

    CPC classification number: H01L29/66795 ,  H01L27/11286 ,  H01L29/0657 ,  H01L29/785

    Abstract: An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

    Abstract translation: 晶体管的一个实施例具有半导体鳍片，半导体鳍片上的电介质，电介质上的控制栅极和半导体鳍片中的源极/漏极，并且在半导体鳍片的最上表面下方具有上表面。 晶体管的另一实施例具有第一和第二半导体鳍片，第一半导体鳍片中的第一源极/漏极区域，并且从第一半导体鳍片的最上表面向下延伸，第二半导体鳍片中的第二源极/漏极区域向下延伸 从所述第二半导体鳍片的最上表面，在所述第一和第二半导体鳍片之间并且邻近所述第一和第二半导体鳍片的侧壁的电介质，以及在所述电介质上方以及所述第一和第二半导体鳍片之间延伸到 在第一和第二源/漏区的上表面以下。

    INTERCONNECTIONS FOR 3D MEMORY
    130.
    发明申请
    INTERCONNECTIONS FOR 3D MEMORY 有权
    三维存储器的互连

    公开(公告)号：US20150340095A1

    公开(公告)日：2015-11-26

    申请号：US14813711

    申请日：2015-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C16/10 ,  G11C16/26 ,  H01L27/115

    CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

    Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

    Abstract translation: 提供了用于3D存储器的互连的装置和方法。 一个示例性设备可以包括包括多对材料的材料堆叠，每对材料包括在绝缘材料上形成的导电线。 一叠材料具有在沿第一方向延伸的一个边缘处形成的阶梯结构。 每个阶梯步骤包括一对材料之一。 第一互连件耦合到阶梯级的导线，第一互连件在基本上垂直于楼梯台阶的第一表面的第二方向上延伸。

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