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    Protected encapsulation of catalytic layer for electroless copper interconnect
    121.
    发明授权
    Protected encapsulation of catalytic layer for electroless copper interconnect 失效
    用于无电铜互连的催化层的保护封装

    公开(公告)号：US5824599A

    公开(公告)日：1998-10-20

    申请号：US587264

    申请日：1996-01-16

    Applicant: Yosef Schacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev ,  Melvin Desilva

    Inventor： Yosef Schacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev ,  Melvin Desilva

    IPC: H01L21/768 ,  H01L21/44

    CPC classification number: H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76858 ,  Y10S977/712 ,  Y10S977/81 ,  Y10S977/888 ,  Y10S977/89

    Abstract: A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.

    Abstract translation: 一种利用无电铜沉积在半导体上形成互连的方法。 一旦在电介质层中形成通孔或沟槽，则沉积氮化钛（TiN）或钽（Ta）阻挡层。 然后，催化铜籽晶层在真空中在阻挡层上共形地覆盖。 接下来，在不破坏真空的情况下，将铝保护层沉积到催化剂层上以包封并保护催化剂层免于氧化。 然后使用无电沉积技术在催化剂层上自动催化沉积铜。 无电沉积溶液溶解上覆的保护层以暴露下面的催化剂层的表面。 无电铜沉积发生在该催化剂表面上，并持续直到通孔/沟槽被填充。 随后，通过施加化学机械抛光（CMP）来抛光铜和阻挡材料，以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。 然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。 铜互连通过TiN（或Ta）阻挡层和覆盖的SiN层从相邻材料完全封装。

    STABILIZED WHOLE GRAIN FLOUR AND METHOD OF MAKING
    125.
    发明申请
    STABILIZED WHOLE GRAIN FLOUR AND METHOD OF MAKING 审中-公开
    稳定的全谷物和制备方法

    公开(公告)号：US20140106052A1

    公开(公告)日：2014-04-17

    申请号：US13985712

    申请日：2012-02-24

    Applicant: Derwin G. Hawley ,  Edward D. Howey ,  William H. Cleaver ,  Lynn C. Haynes ,  Desiree S. Bramble ,  Ning Zhou ,  Bin Zhao ,  Timothy S. Hansen ,  Domenico R. Cassone ,  Sarwat Gabriel

    Inventor： Derwin G. Hawley ,  Edward D. Howey ,  William H. Cleaver ,  Lynn C. Haynes ,  Desiree S. Bramble ,  Ning Zhou ,  Bin Zhao ,  Timothy S. Hansen ,  Domenico R. Cassone ,  Sarwat Gabriel

    IPC: A21D6/00

    CPC classification number: A21D6/003 ,  A21D13/02 ,  A23L7/115 ,  A23L7/197 ,  B02C9/04 ,  B02C23/08

    Abstract: Stabilized whole grain flours having a fine particle size and which exhibit good baking functionality are produced with high throughput using two bran and germ fractions and an endosperm fraction. One bran and germ fraction is a coarse fraction which is subjected to two stage grinding, but the second bran and germ fraction is a low ash, fine bran and germ fraction which is sufficiently fine so that it does not need to be subjected to grinding thereby reducing starch damage and increasing production with reduced grinding equipment load. Portions of the coarse bran and germ fraction which are ground in the first grinding stage to a sufficient fineness are separated out and not subjected to additional grinding further reducing starch damage and increasing production. The bran and germ fractions may be combined, subjected to stabilization, and combined with the endosperm fraction to obtain a stabilized whole grain flour.

    Abstract translation: 使用两个麸皮和胚芽部分和胚乳部分以高产量生产具有细粒度并且表现出良好烘烤功能的稳定的全谷物面粉。 一个麸皮和胚芽部分是经过两阶段研磨的粗级分，但是第二糠和胚芽级分是足够细的低灰分，细糠和胚芽分数，从而不需要进行研磨 降低粉碎设备负荷，减少淀粉损伤并增加生产。 将在第一研磨阶段研磨的粗糠和胚芽级分的部分分离成足够的细度，并且不进行另外的研磨，进一步减少淀粉损伤并增加产量。 可以将麸皮和胚芽部分组合，进行稳定化，并与胚乳部分组合以获得稳定的全谷物粉末。

    VLPs derived from cells that do not express a viral matrix or core protein
    126.
    发明授权
    VLPs derived from cells that do not express a viral matrix or core protein 有权
    源自不表达病毒基质或核心蛋白的细胞的VLP

    公开(公告)号：US08697088B2

    公开(公告)日：2014-04-15

    申请号：US12127625

    申请日：2008-05-27

    Applicant: Gale Smith ,  Peter Pushko ,  Kutub Mahmood ,  Bin Zhao

    Inventor： Gale Smith ,  Peter Pushko ,  Kutub Mahmood ,  Bin Zhao

    IPC: A61K39/145 ,  C12N15/44

    CPC classification number: A61K39/145 ,  A61K2039/5258 ,  C07K2319/00 ,  C12N7/00 ,  C12N2710/16723 ,  C12N2760/16123

    Abstract: The present invention discloses novel influenza virus-like particles (VLPs) that contain chimeric proteins or influenza membrane proteins. The chimeric proteins are derived from fragments of influenza membrane proteins fused to heterologous proteins. The invention includes antigenic formulations and vaccines comprising VLPs of the invention as well as methods of making and administering VLPs to vertebrates, including methods of inducing immunity to infections, such as influenza.

    Abstract translation: 本发明公开了含有嵌合蛋白或流感病毒膜蛋白的新型流感病毒样颗粒（VLPs）。 嵌合蛋白质衍生自与异源蛋白质融合的流感病毒膜蛋白片段。 本发明包括抗原制剂和包含本发明的VLP的疫苗以及向脊椎动物制备和施用VLP的方法，包括诱导感染免疫的方法，例如流感。

    Serial cascade of minimium tail voltages of subsets of LED strings for dynamic power control in LED displays
    129.
    发明授权
    Serial cascade of minimium tail voltages of subsets of LED strings for dynamic power control in LED displays 有权
    用于LED显示屏中动态功率控制的LED灯串子串的最小尾电压串联级联

    公开(公告)号：US08493003B2

    公开(公告)日：2013-07-23

    申请号：US12690972

    申请日：2010-01-21

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H05B37/02

    CPC classification number: H05B33/0818 ,  H05B33/0857

    Abstract: A light emitting diode (LED) system implements a power management technique. The LED system includes a plurality of LED drivers connected in series, each LED driver configured to regulate the current flowing through a corresponding subset of a plurality of LED strings. Each LED driver determines the tail voltages of the one or more LED strings of the corresponding subset. Each LED driver, except for the first LED driver in the series, also receives a voltage representative of the minimum tail voltage of the other subsets regulated by the upstream LED drivers. Each LED driver then provides the lowest of the voltage received from the upstream LED driver and the one or more tail voltages of the corresponding subset to the downstream LED driver. In this manner a voltage representative of the minimum tail voltage of the plurality of LED strings is cascaded through the series. A feedback controller monitors the minimum tail voltage represented by this cascaded voltage and accordingly adjusts an output voltage provided to the head ends of the plurality of LED strings.

    Abstract translation: 发光二极管（LED）系统实现电源管理技术。 LED系统包括串联连接的多个LED驱动器，每个LED驱动器配置成调节流过多个LED串的相应子集的电流。 每个LED驱动器确定相应子集的一个或多个LED串的尾部电压。 除了该系列中的第一个LED驱动器之外，每个LED驱动器还接收代表由上游LED驱动器调节的其他子集的最小尾电压的电压。 然后，每个LED驱动器将从上游LED驱动器接收的最低电压和相应子集的一个或多个尾部电压提供给下游LED驱动器。 以这种方式，表示多个LED串的最小尾电压的电压通过该系列级联。 反馈控制器监视由该级联电压表示的最小尾电压，并相应地调节提供给多个LED串的头端的输出电压。

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