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    Memory controller with clock-to-strobe skew compensation
    121.
    发明授权
    Memory controller with clock-to-strobe skew compensation 有权
    具有时钟到频闪偏移补偿的存储控制器

    公开(公告)号：US09437279B2

    公开(公告)日：2016-09-06

    申请号：US14951190

    申请日：2015-11-24

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C7/22 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G11C7/10 ,  G06F1/10 ,  G11C11/409

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

    Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

    Abstract translation: 时钟信号通过时钟信号线发送到第一和第二集成电路（IC）组件，该时钟信号在第一IC组件处具有第一到达时间，而在第二IC组件处具有第二较晚的到达时间。 在对应于时钟信号的转变的各个时刻，写入命令被发送到要被这些分量采样的第一和第二IC组件，并且与写命令相关联地将写数据发送到第一和第二IC组件。 第一和第二选通信号分别被发送到第一和第二IC组件，以便在这些组件中对第一和第二写入数据进行时间接收。 从多个相位偏移定时信号中选择第一和第二选通信号，以补偿时钟信号与第一和第二选通信号之间的各自的定时偏差。

    MEMORY COMPONENT HAVING INTERNAL READ MODIFY-WRITE OPERATION
    124.
    发明申请
    MEMORY COMPONENT HAVING INTERNAL READ MODIFY-WRITE OPERATION 有权
    具有内部读取修改操作的存储组件

    公开(公告)号：US20160231962A1

    公开(公告)日：2016-08-11

    申请号：US15022176

    申请日：2014-09-23

    Applicant: RAMBUS INC.

    Inventor： Frederick A. Ware ,  Thomas Vogelsang

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

    Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

    Abstract translation: 存储器组件包括存储器组和用于接收读取 - 修改 - 写入命令的命令接口，其具有指示存储器组中的位置的相关联的读取地址，以及从读取的指示的存储器组中的位置访问读取数据 从接收到读 - 修改 - 写入命令的时间开始，或者与多个读 - 修改 - 写入命令重叠，可调节延迟时间之后的地址。 存储器组件还包括用于接收与读取 - 修改 - 写入命令相关联的写入数据的数据接口和用于将接收到的写入数据与读取的数据合并以形成合并数据的纠错电路，并将合并的数据写入到 由读取地址指示的存储体。

    IN-BAND STATUS ENCODING AND DECODING USING ERROR CORRECTION SYMBOLS
    126.
    发明申请
    IN-BAND STATUS ENCODING AND DECODING USING ERROR CORRECTION SYMBOLS 有权
    使用错误校正符号进行带内状态编码和解码

    公开(公告)号：US20160056842A1

    公开(公告)日：2016-02-25

    申请号：US14814206

    申请日：2015-07-30

    Applicant: Rambus Inc.

    Inventor： John Eric Linstadt ,  Frederick A. Ware

    IPC: H03M13/15 ,  H03M13/09 ,  G06F11/10

    CPC classification number: H04L1/0047 ,  G06F11/1004 ,  H03M13/1515 ,  H03M13/1575 ,  H03M13/19

    Abstract: A status encoder generates a checksum that encodes a status condition together with the checksum of an associated message. A receiver determines an inverse transformation that when applied to the received status-encoded checksum recovers the parity information associated with the codeword. The status condition can then be recovered based on the selection of the inverse transformation that correctly recovers the parity information from the status-encoded checksum. Beneficially, the status condition can be encoded without requiring additional signal lines or lengthening the codeword relative to conventional error correction devices.

    Abstract translation: 状态编码器生成校验和，其将状态条件与相关消息的校验和一起编码。 接收机确定当应用于接收到的状态编码校验和时恢复与码字相关联的奇偶校验信息的逆变换。 然后可以基于从状态编码的校验和正确地恢复奇偶校验信息的逆变换的选择来恢复状态条件。 有利的是，可以编码状态条件，而不需要额外的信号线或相对于传统的纠错装置来延长码字。

    System and module comprising an electrically erasable programmable memory chip
    127.
    发明授权
    System and module comprising an electrically erasable programmable memory chip 有权
    包括电可擦除可编程存储器芯片的系统和模块

    公开(公告)号：US09262269B2

    公开(公告)日：2016-02-16

    申请号：US14836467

    申请日：2015-08-26

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang ,  Frederick A. Ware

    IPC: G11C29/00 ,  G06F11/00 ,  G06F11/14 ,  H03M13/29 ,  G06F11/10

    CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

    Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

    Memory device with retransmission upon error
    128.
    发明授权
    Memory device with retransmission upon error 有权
    存储设备错误重传

    公开(公告)号：US09262262B2

    公开(公告)日：2016-02-16

    申请号：US14853869

    申请日：2015-09-14

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang ,  Frederick A. Ware

    IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09

    CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

    Abstract: A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

    Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

    Memory Controller With Error Detection And Retry Modes Of Operation
    129.
    发明申请
    Memory Controller With Error Detection And Retry Modes Of Operation 审中-公开
    具有错误检测和重试操作模式的内存控制器

    公开(公告)号：US20160004597A1

    公开(公告)日：2016-01-07

    申请号：US14855271

    申请日：2015-09-15

    Applicant: Rambus Inc.

    Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

    Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

    Abstract translation: 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

    Memory controller with clock-to-strobe skew compensation
    130.
    发明授权
    Memory controller with clock-to-strobe skew compensation 有权

    公开(公告)号：US09229470B2

    公开(公告)日：2016-01-05

    申请号：US14267446

    申请日：2014-05-01

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C7/10 ,  G06F12/00 ,  G06F1/10 ,  G11C7/22 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

    Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

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