公开(公告)号：US20150037932A1

公开(公告)日：2015-02-05

申请号：US14459597

申请日：2014-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

Abstract translation: 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

公开(公告)号：US20140327007A1

公开(公告)日：2014-11-06

申请号：US14334012

申请日：2014-07-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

IPC: H01L27/12 ,  H01L27/088

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

Abstract translation: 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面提供并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

公开(公告)号：US20140284595A1

公开(公告)日：2014-09-25

申请号：US14204365

申请日：2014-03-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Taiga MURAOKA

IPC: H01L29/786 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02521 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/78618 ,  H01L29/78666 ,  H01L29/78675 ,  H01L29/78696

Abstract: A semiconductor device for miniaturization is provided. The semiconductor device includes a semiconductor layer; a first electrode and a second electrode that are on the semiconductor layer and apart from each other over the semiconductor layer; a gate electrode over the semiconductor layer; and a gate insulating layer between the semiconductor layer and the gate electrode. The first and second electrodes comprise first conductive layers and second conductive layers. In a region overlapping with the semiconductor layer, the second conductive layers are positioned between the first conductive layers, and side surfaces of the second conductive layers are in contact with side surfaces of the first conductive layers. The second conductive layers have smaller thicknesses than those of the first conductive layers, and the top surface levels of the second conductive layers are lower than those of the first conductive layers.

Abstract translation: 提供了一种用于小型化的半导体器件。 半导体器件包括半导体层; 在所述半导体层上并且在所述半导体层上彼此分开的第一电极和第二电极; 半导体层上的栅电极; 以及在半导体层和栅电极之间的栅极绝缘层。 第一和第二电极包括第一导电层和第二导电层。 在与半导体层重叠的区域中，第二导电层位于第一导电层之间，第二导电层的侧表面与第一导电层的侧表面接触。 所述第二导电层的厚度小于所述第一导电层的厚度，并且所述第二导电层的顶表面电平低于所述第一导电层的顶表面电平。

公开(公告)号：US20140127868A1

公开(公告)日：2014-05-08

申请号：US14151036

申请日：2014-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.

Abstract translation: 提供了一种小型化的晶体管，其产率高。 此外，提供了具有高导通状态特性并且能够进行高速响应和高速操作的半导体器件。 在半导体装置中，依次层叠氧化物半导体层，栅极绝缘层，栅极电极层，绝缘层，导电膜和层间绝缘层。 通过切割导电膜以自对准的方式形成源电极层和漏电极层，从而去除栅极电极层和导电层上的导电膜，并且导电膜被分割。 设置与氧化物半导体层接触并与与源极电极层和漏极电极层接触的区域重叠的电极层。

公开(公告)号：US20140051209A1

公开(公告)日：2014-02-20

申请号：US14062000

申请日：2013-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66 ,  H01L21/44

CPC classification number: H01L27/1262 ,  H01L21/44 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.

Abstract translation: 描述了一种用于制造半导体器件的方法。 在绝缘膜上形成掩模，并且掩模的尺寸减小。 使用尺寸减小的掩模形成具有突起的绝缘膜，并且使用具有突起的绝缘膜形成沟道长度减小的晶体管。 此外，在制造晶体管时，在与微细突起的顶面重叠的栅极绝缘膜的表面上进行平坦化处理。 因此，晶体管可以高速运转，可提高可靠性。 此外，绝缘膜被加工成具有突起的形状，由此可以以自对准的方式形成源电极和漏电极。

公开(公告)号：US20130161621A1

公开(公告)日：2013-06-27

申请号：US13716899

申请日：2012-12-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Yutaka OKAZAKI ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L27/10879 ,  H01L27/1104 ,  H01L27/11521 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Abstract translation: 在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜，通过使用经受电子束曝光的抗蚀剂选择性蚀刻第一导电膜形成栅电极，在栅绝缘膜上形成第一绝缘膜 和栅电极，在栅电极未被露出的同时去除第一绝缘膜的一部分，在第一绝缘膜，抗反射膜，第一绝缘膜和栅极绝缘膜上形成防反射膜 使用经受电子束曝光的抗蚀剂选择性蚀刻，以及与氧化物半导体膜的一端接触的源极和与氧化物半导体膜的另一端接触的第一绝缘膜和漏电极的一端，以及 形成第一绝缘膜的另一端。

公开(公告)号：US20130092924A1

公开(公告)日：2013-04-18

申请号：US13632603

申请日：2012-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78606 ,  H01L27/1156 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

Abstract translation: 提供具有优异电特性的小型化晶体管，其产率高。 此外，以高生产率制造包括晶体管并且具有高性能和高可靠性的半导体器件。 在包括晶体管的半导体器件中，其中包括沟道形成区域的氧化物半导体膜和夹在沟道形成区域之间的低电阻区域，栅极绝缘膜和顶表面和侧表面被覆盖的栅极电极层 堆叠具有氧化铝膜的绝缘膜，源极电极层和漏电极层与氧化物半导体膜的一部分和顶面以及包含氧化铝膜的绝缘膜的侧面接触。

公开(公告)号：US20240404884A1

公开(公告)日：2024-12-05

申请号：US18799170

申请日：2024-08-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tsutomu MURAKAWA ,  Shinya SASAGAWA ,  Naoto YAMADE ,  Takashi HAMADA ,  Hiroki KOMAGATA

IPC: H01L21/8234 ,  H01L21/225 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/786

Abstract: To provide a semiconductor device with less variations, a first insulator is deposited; a stack of first and second oxides and a first conductor is formed over the first insulator; a second insulator is formed over the first insulator and the stack; an opening is formed in the second insulator; a top surface of the second oxide is exposed by removing a region of the first conductor, second and third conductors are formed over the second oxide, and then cleaning is performed; a first oxide film is deposited in contact with a side surface of the first oxide and top and side surfaces of the second oxide; heat treatment is performed on an interface between the second oxide and the first oxide film through the first oxide film; and the second insulator is exposed and a fourth conductor, a third insulator, and a third oxide are formed in the opening.

公开(公告)号：US20240381704A1

公开(公告)日：2024-11-14

申请号：US18578093

申请日：2022-06-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shinya SASAGAWA ,  Ryota HODO ,  Kentaro SUGAYA ,  Yoshikazu HIURA ,  Takahiro FUJIE

IPC: H10K59/124 ,  H10K59/12 ,  H10K71/20 ,  H10K71/40

Abstract: A display apparatus with high display quality is provided. The display apparatus includes a first light-emitting device, a second light-emitting device, a first insulating layer, and a second insulating layer. The first light-emitting device includes a first pixel electrode, a first light-emitting layer over the first pixel electrode, and a common electrode over the first light-emitting layer. The second light-emitting device includes a second pixel electrode, a second light-emitting layer over the second pixel electrode, and the common electrode over the second light-emitting layer. The first insulating layer covers a side surface and part of a top surface of the first light-emitting layer and a side surface and part of a top surface of the second light-emitting layer. The second insulating layer overlaps with the side surface and the part of the top surface of the first light-emitting layer and the side surface and the part of the top surface of the second light-emitting layer with the first insulating layer therebetween. The common electrode covers the second insulating layer. In a cross-sectional view, an end portion of the second insulating layer has a tapered shape with a taper angle less than 90°. The second insulating layer covers at least part of a side surface of the first insulating layer.

公开(公告)号：US20240315084A1

公开(公告)日：2024-09-19

申请号：US18575971

申请日：2022-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Ryota HODO ,  Kentaro SUGAYA ,  Yoshikazu HIURA ,  Takahiro FUJIE

IPC: H10K59/122 ,  H10K59/12 ,  H10K59/35

CPC classification number: H10K59/122 ,  H10K59/1201 ,  H10K59/35

Abstract: A display apparatus with high display quality is provided. The display apparatus includes a first light-emitting device including a first pixel electrode, a first layer, and a common electrode; a second light-emitting device including a second pixel electrode, a second layer, and the common electrode; a first coloring layer; a second coloring layer transmitting light with a color different from a color of light transmitted by the first coloring layer; a first insulating layer; and a second coloring layer. The first layer and the second layer each contain a first light-emitting material emitting blue light and a second light-emitting material emitting light with a longer wavelength than blue light and are separated from each other. The first insulating layer covers a side surface and part of a top surface of the first layer and a side surface and part of a top surface of the second layer. The second insulating layer overlaps with the side surface and the part of the top surface of the first layer and the side surface and the part of the top surface of the second layer with the first insulating layer therebetween. The common electrode covers the second insulating layer. In a cross-sectional view, an end portion of the second insulating layer has a tapered shape with a taper angle less than 90 degrees.