公开(公告)号：US20240211023A1

公开(公告)日：2024-06-27

申请号：US18146811

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Shang Yang

IPC: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/45

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

公开(公告)号：US12019566B2

公开(公告)日：2024-06-25

申请号：US16938364

申请日：2020-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sergey Blagodurov ,  Johnathan Alsop ,  Jagadish B. Kotra ,  Marko Scrbak ,  Ganesh Dasika

IPC: G06F13/16 ,  G06F9/30 ,  H04L45/122

CPC classification number: G06F13/1642 ,  G06F9/3004 ,  G06F9/30098 ,  G06F13/1663 ,  H04L45/122

Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.

公开(公告)号：US20240203036A1

公开(公告)日：2024-06-20

申请号：US18083298

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： John Alexandre Tsakok

IPC: G06T15/08 ,  G06T15/10

CPC classification number: G06T15/08 ,  G06T15/10 ,  G06T2210/12

Abstract: A technique for building a bounding volume hierarchy is disclosed. The technique subdividing a candidate box node based on a resolution to generate a plurality of cells of the candidate box node; identifying a plurality of nodes of a triangle set collection that fit within the cells; generating a plurality of candidate splits based on the plurality of nodes; selecting a candidate split based on a selection criterion to obtain a selected candidate split; and generating child box nodes for a box node of a bounding volume hierarchy under construction, based on the selected candidate split.

公开(公告)号：US20240202121A1

公开(公告)日：2024-06-20

申请号：US18068670

申请日：2022-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  Nuwan S Jayasena

IPC: G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: Programmable data storage memory hierarchy techniques are described. In one example, a data storage system includes a memory hierarchy and a data movement controller. The memory hierarchy includes a hierarchical arrangement of a plurality of memory buffers. The data movement controller is configured to receive a data movement command and control data movement between the plurality of memory buffers based on the data movement command.

公开(公告)号：US20240202015A1

公开(公告)日：2024-06-20

申请号：US18066155

申请日：2022-12-14

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Lu Lu ,  Anthony Asaro ,  Gia Tung Phan ,  Gongxian Cheng ,  Philip Ng ,  Yinan Jiang ,  Felix Kuehling

IPC: G06F9/455 ,  G06F9/54

CPC classification number: G06F9/45545 ,  G06F9/45558 ,  G06F9/545 ,  G06F2009/4557 ,  G06F2009/45579

Abstract: In a computing device, a hardware device (e.g., a parallel accelerated processor or graphics processing unit) is coupled to a bus, such as a peripheral component interconnect express (PCIe) bus. The hardware device supports physical partitioning that allows physical resources of the hardware device to be separated into different partitions. Examples of such physical resources include engine resources (e.g., compute resources, direct memory access resources), memory resources (e.g., random access memory), and so forth. Each physical partition is mapped to a physical function that is exposed to a host on the computing device in a manner that is compliant with the bus protocol, allowing software to access the physical partition in a conventional manner based on the bus protocol.

公开(公告)号：US20240201993A1

公开(公告)日：2024-06-20

申请号：US18067506

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Dilawarhusen Aga ,  Leopold Grinberg

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/345 ,  G06F9/3877

Abstract: Data evaluation using processing-in-memory is described. In accordance with the described techniques, data evaluation logic is loaded into a processing-in-memory component. The processing-in-memory component executes the data evaluation logic to evaluate a minimum number of bits required to retrieve data from, or store data to, at least one memory location. A result is output indicating the number of bits required to represent data at the at least one memory location based on the evaluation.

公开(公告)号：US20240201777A1

公开(公告)日：2024-06-20

申请号：US18084499

申请日：2022-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： James Mossman ,  Robert Cohen ,  Sudherssen Kalaiselvan ,  Tzu-Wei Lin

IPC: G06F1/3296 ,  G06F1/3287

CPC classification number: G06F1/3296 ,  G06F1/3287

Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12014213B2

公开(公告)日：2024-06-18

申请号：US16564388

申请日：2019-09-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Daniel L. Bouvier

IPC: G06F9/50 ,  G06F1/3234 ,  G06F9/4401 ,  G06F12/02 ,  G06F12/1009 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G06F9/5016 ,  G06F1/3275 ,  G06F9/4418 ,  G06F9/442 ,  G06F12/0238 ,  G06F12/1009 ,  G11C11/406 ,  G11C11/4074 ,  G06F2212/657

Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.

公开(公告)号：US12013810B2

公开(公告)日：2024-06-18

申请号：US17956013

申请日：2022-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas

IPC: G06F15/80 ,  G06F15/76 ,  G06T15/00

CPC classification number: G06F15/80 ,  G06T15/005 ,  G06F2015/765

Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.

公开(公告)号：US20240196033A1

公开(公告)日：2024-06-13

申请号：US18078603

申请日：2022-12-09

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Yuping Shen ,  Min Zhang

IPC: H04N21/262 ,  H04N19/164 ,  H04N19/172 ,  H04N21/658

CPC classification number: H04N21/2625 ,  H04N19/164 ,  H04N19/172 ,  H04N21/658

Abstract: In a cloud gaming system or other remote video streaming system, a client device and a server coordinate to introduce an adjustable delay in the frame start timing in the frame rendering pipeline at the server to reducing vertical synchronization (VSYNC) presentation latency, and thus reduce overall frame latency. In implementations, the coordination between the client device and the server includes the client device observing the current VSYNC presentation latencies in recently processed video frames reporting this observed VSYNC presentation latency to the server. The server uses this feedback to determine a frame start delay that is then used to introduce a frame start shift for an upcoming frame and subsequent frames, thereby shifting the server rendering and encoding pipeline back so that the resulting video frames are made available to present at the client device closer to their respective VSYNC signal assertions.