公开(公告)号：US20110169076A1

公开(公告)日：2011-07-14

申请号：US12685644

申请日：2010-01-11

申请人： Yi-Chi Chang ,  Chia-Lien Wu

发明人： Yi-Chi Chang ,  Chia-Lien Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/511 ,  H01L29/66734 ,  H01L29/7811

摘要： A power MOSFET is described. A trench is in a body layer and an epitaxial layer. An isolation structure is on the substrate at one side of the trench. An oxide layer is on the surface of the trench. A first conductive layer fills the trench and extends to the isolation structure. A dielectric layer is on the first conductive layer and isolation structure and has an opening exposing the first conductive layer. At least one source region is in the body layer at the other side of the trench. A second conductive layer is on the dielectric layer and electrically connected to the source region while electrically isolated from the first conductive layer by the dielectric layer. A third conductive layer is on the dielectric layer and electrically connected to the first conductive layer through the opening of the dielectric layer. The second and third conductive layers are separated.

摘要翻译： 描述功率MOSFET。 沟槽在体层和外延层中。 隔离结构位于沟槽一侧的衬底上。 氧化层位于沟槽表面。 第一导电层填充沟槽并延伸到隔离结构。 电介质层位于第一导电层和隔离结构上，并具有暴露第一导电层的开口。 至少一个源区位于沟槽另一侧的体层中。 第二导电层在电介质层上并且电连接到源极区，同时通过电介质层与第一导电层电隔离。 第三导电层位于电介质层上，并通过电介质层的开口与第一导电层电连接。 第二和第三导电层被分离。

公开(公告)号：US20110076818A1

公开(公告)日：2011-03-31

申请号：US12962499

申请日：2010-12-07

申请人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

发明人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US20100320533A1

公开(公告)日：2010-12-23

申请号：US12868698

申请日：2010-08-25

申请人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

发明人： HIROSHI INAGAWA ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L29/78

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体衬底的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US07651910B2

公开(公告)日：2010-01-26

申请号：US10150623

申请日：2002-05-17

申请人： Kevin L. Beaman ,  Ronald A. Weimer

发明人： Kevin L. Beaman ,  Ronald A. Weimer

IPC分类号： H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/518

摘要： The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed over the tunnel oxide. The stack comprises a floating gate, dielectric mass and control gate. The stack has a top, and has opposing sidewalls extending downwardly from the top. The dielectric mass includes silicon nitride. Silicon nitride spacers are formed along sidewalls of the stack, and a silicon nitride cap is formed over a top of the stack. The silicon nitride within the dielectric mass, cap and/or sidewall spacers is formed from trichlorosilane and ammonia.

摘要翻译： 本发明包括一种形成可编程存储器件的方法。 隧道氧化物形成为被半导体衬底支撑。 在隧道氧化物上形成堆叠。 该堆叠包括浮动栅极，介电质量块和控制栅极。 堆叠具有顶部，并且具有从顶部向下延伸的相对侧壁。 介电质量包括氮化硅。 氮化硅间隔物沿着堆叠的侧壁形成，并且在堆叠的顶部上形成氮化硅帽。 介电体内的氮化硅，帽和/或侧壁间隔物由三氯硅烷和氨形成。

公开(公告)号：US07622763B2

公开(公告)日：2009-11-24

申请号：US10565624

申请日：2004-07-28

申请人： Jun Suda ,  Hiroyuki Matsunami

发明人： Jun Suda ,  Hiroyuki Matsunami

IPC分类号： H01L29/792

CPC分类号： H01L21/28158 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/802 ,  H01L29/803

摘要： A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO2 layer formed thereon, and a gate electrode 15 formed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

摘要翻译： 场效应晶体管包括SiC衬底1，形成在SiC衬底1的表面上的源极3a和漏极3b，绝缘结构，其包括与SiC表面接触形成的AlN层5， 层或更大，以及形成在其上的SiO 2层，以及形成在绝缘结构上的栅电极15。 可以控制漏电流，同时与SiC的界面状态保持良好状态。

公开(公告)号：US07585725B2

公开(公告)日：2009-09-08

申请号：US12204603

申请日：2008-09-04

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide -nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

公开(公告)号：US07564098B2

公开(公告)日：2009-07-21

申请号：US11798930

申请日：2007-05-17

申请人： Wataru Sumida

发明人： Wataru Sumida

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66734

摘要： In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

摘要翻译： 在半导体器件中，在半导体晶片的沟槽内形成栅极二氧化硅层。 第一栅电极经由栅极二氧化硅层形成在半导体晶片的沟槽的侧壁上。 绝缘层经由栅极二氧化硅层形成在半导体晶片的沟槽的底部上并被第一栅电极包围。 绝缘层不包括二氧化硅，并且具有与二氧化硅不同的蚀刻特性。 第二栅电极被埋在半导体晶片的沟槽中，并与第一栅电极和绝缘层接触。

公开(公告)号：US20090160017A1

公开(公告)日：2009-06-25

申请号：US12285577

申请日：2008-10-09

申请人： Hiroyasu Ito

发明人： Hiroyasu Ito

IPC分类号： H01L29/86 ,  H01L21/20

CPC分类号： H01L29/94 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/3185 ,  H01L27/0658 ,  H01L27/0682 ,  H01L29/045 ,  H01L29/511 ,  H01L29/7322

摘要： In manufacturing a semiconductor device including a substrate having a (111)-plane orientation and an off-set angle in a range between 3 degrees and 4 degrees, a capacitor, a transistor and a diffusion resistor are formed in the substrate, each of which are separated by a junction separation layer. A first silicon nitride film is formed by low pressure CVD over a surface of the substrate except a bottom portion of a contact hole and a portion over the junction separation layer, and a silicon oxide film is formed by low pressure CVD over the first silicon nitride film. A second silicon nitride film as a protecting film is formed by plasma CVD so as to cover the semiconductor device finally. Therefore, the semiconductor device having high reliability can be obtained.

摘要翻译： 在制造包括具有（111）平面取向的基板和在3度和4度之间的范围内的偏移角的半导体器件时，在基板中形成电容器，晶体管和扩散电阻器，每个电容器 被连接分离层分离。 通过低压CVD在基板的表面上形成第一氮化硅膜，除了接触孔的底部和接合分离层之上的部分之外，并且通过低压CVD在第一氮化硅上形成氧化硅膜 电影。 通过等离子体CVD形成作为保护膜的第二氮化硅膜，以最终覆盖半导体器件。 因此，可以获得具有高可靠性的半导体器件。

公开(公告)号：US07528037B2

公开(公告)日：2009-05-05

申请号：US11209128

申请日：2005-08-22

申请人： Leonard Forbes

发明人： Leonard Forbes

IPC分类号： H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/517

摘要： A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator.

摘要翻译： 在快闪存储单元中使用高介电常数隧道电介质，以较小的栅极电压向浮栅提供更大的隧道电流。 闪存单元具有具有源极/漏极区域的衬底。 高k隧道电介质形成在衬底上。 可以使用蒸发技术或原子层沉积技术来沉积高k隧道电介质。 浮置栅极形成在高k电介质层的顶部，氧化物栅极绝缘体在其顶部。 在顶栅极绝缘体上形成多晶硅控制栅极。

公开(公告)号：US07521326B2

公开(公告)日：2009-04-21

申请号：US11285142

申请日：2005-11-23

申请人： Koichiro Tanaka

发明人： Koichiro Tanaka

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/268 ,  H01L21/823814 ,  H01L29/4958 ,  H01L29/511 ,  H01L29/6653

摘要： It is an object of the present invention to provide a semiconductor device superior in the decrease in leak current due to a short-channel effect and a manufacturing method thereof. In a process of forming a field-effect transistor over a single-crystal semiconductor substrate, an impurity is introduced to form an extension region and a single crystal lattice is broken to make the extension region amorphous. Alternatively, the impurity and an element having large mass number are introduced to break the single crystal lattice and make the extension region amorphous. Then, a laser beam with a pulse width of 1 fs to 10 ps and a wavelength of 370 to 640 nm is delivered to selectively activate the amorphous portion, so that the extension region is formed with a thickness of 20 nm or less.

摘要翻译： 本发明的目的是提供一种由于短路效应而导致的漏电流下降优异的半导体器件及其制造方法。 在单晶半导体衬底上形成场效应晶体管的过程中，引入杂质以形成延伸区域，并且单晶晶格被破坏以使得延伸区域变为无定形。 或者，引入杂质和质量大的元素以破坏单晶晶格并使延伸区域成为无定形的。 然后，输送脉冲宽度为1fs至10ps且波长为370至640nm的激光束以选择性地激活非晶部分，使得延伸区域形成为20nm或更小的厚度。