公开(公告)号：US20240395941A1

公开(公告)日：2024-11-28

申请号：US18792762

申请日：2024-08-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masahiro TAKAHASHI ,  Tatsuya HONDA ,  Takehisa HATANO

IPC: H01L29/786 ,  H01L29/00 ,  H01L29/04 ,  H01L29/12 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/772

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

公开(公告)号：US20240395825A1

公开(公告)日：2024-11-28

申请号：US18789755

申请日：2024-07-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Wataru UESUGI ,  Hikaru TAMURA ,  Atsuo ISOBE

IPC: H01L27/12 ,  G11C7/04 ,  H01L29/04 ,  H01L29/78 ,  H01L29/786 ,  H03K19/00 ,  H03K19/0185

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US12156410B2

公开(公告)日：2024-11-26

申请号：US17629804

申请日：2020-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Tatsuya Onuki ,  Yuki Okamoto ,  Hideki Uochi ,  Satoru Okamoto ,  Hiromichi Godo ,  Kazuki Tsuda ,  Hitoshi Kunitake

IPC: H10B63/00 ,  H10B41/27 ,  H10B43/27

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US12154909B2

公开(公告)日：2024-11-26

申请号：US18229226

申请日：2023-08-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kei Takahashi ,  Yoshiyuki Kurokawa

IPC: H01L27/12 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  H01L29/24 ,  H01L29/786

Abstract: A display device that is suitable for increasing its size is provided. The display device includes first to third wirings, a first transistor, first to third conductive layers, and a first pixel electrode; the first wiring extends in a first direction and intersects with the second and the third wirings; the second and the third wirings each extend in a second direction intersecting with the first direction; a gate of the first transistor is electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring through the first to the third conductive layers; the second conductive layer includes a region overlapping with the third wiring; the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material; the first wiring and the second conductive layer contain the same material; the first wiring is supplied with a selection signal; and the second and the third wirings are supplied with different signals.

公开(公告)号：US20240389295A1

公开(公告)日：2024-11-21

申请号：US18785940

申请日：2024-07-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takayuki Ikeda ,  Kiyoshi Kato ,  Yuta Endo ,  Junpei Sugao

IPC: H10B12/00 ,  G11C5/02 ,  G11C11/403 ,  G11C11/409 ,  H01L29/24

Abstract: A semiconductor device with a large storage capacity per unit area is provided.
A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

公开(公告)号：US20240381687A1

公开(公告)日：2024-11-14

申请号：US18692944

申请日：2022-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Nobuharu OHSAWA ,  Toshiki SASAKI ,  Shinya SASAGAWA ,  Ryota HODO ,  Kentaro SUGAYA ,  Yoshikazu HIURA ,  Takahiro FUJIE

IPC: H10K50/17 ,  H10K50/13 ,  H10K50/16 ,  H10K50/19 ,  H10K59/122 ,  H10K59/35 ,  H10K59/80 ,  H10K85/60 ,  H10K101/20 ,  H10K101/30

Abstract: A novel display apparatus that is highly convenient, useful, or reliable is provided. The display apparatus includes a first light-emitting device, a second light-emitting device, a first insulating layer, and a second insulating layer. The first light-emitting device includes a first pixel electrode, a common electrode, and a first intermediate layer. The first intermediate layer includes a first inorganic compound and a first organic compound. The first organic compound has an unshared electron pair. The first organic compound interacts with the first inorganic compound to form a singly occupied molecular orbital. The second light-emitting device includes a second pixel electrode, the common electrode, and a second intermediate layer. The second intermediate layer includes the first inorganic compound and the first organic compound. The first insulating layer covers a side surface and part of a top surface of the first intermediate layer and a side surface and part of a top surface of the second intermediate layer. The second insulating layer overlaps with the side surface and the part of the top surface of the first intermediate layer and the side surface and the part of the top surface of the second intermediate layer with the first insulating layer therebetween.

公开(公告)号：US20240379941A1

公开(公告)日：2024-11-14

申请号：US18576873

申请日：2022-06-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jo SAITO ,  Tatsuyoshi TAKAHASHI ,  Kunihiko SUZUKI ,  Shunsuke HOSOUMI ,  Mayumi MIKAMI ,  Kazuki TANEMURA ,  Yuji IWAKI ,  Shunpei YAMAZAKI

IPC: H01M4/36 ,  C01G51/00 ,  H01M4/02 ,  H01M4/1315 ,  H01M4/525 ,  H01M10/0525

Abstract: A positive electrode active material that is unlikely to generate defects even when charging and discharging at a high voltage and/or at a high temperature is provided. A positive electrode active material in which crystal structures are unlikely to collapse even when charging and discharging are repeated is also provided. The positive electrode active material contains lithium, cobalt, oxygen, and an additive element. The positive electrode active material includes a surface portion, an inner portion. The positive electrode active material contains the additive element in the surface portion. The surface portion is a region extending from a surface of the positive electrode active material to a depth of 10 nm or less toward the inner portion, and the surface portion and the inner portion are topotaxy. A degree of diffusion of the additive element vary between crystal planes of the surface portion, and the additive element is at least one or two or more selected from nickel, aluminum, and magnesium.

公开(公告)号：US12142759B2

公开(公告)日：2024-11-12

申请号：US17291463

申请日：2019-11-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Mayumi Mikami ,  Yohei Momma ,  Teruaki Ochiai

IPC: H01M4/525 ,  H01M4/02 ,  H01M4/505 ,  H01M10/0525

Abstract: A positive electrode active material with high capacity and excellent charging and discharging cycle performance for a lithium-ion secondary battery is provided. The positive electrode active material contains lithium, cobalt, and oxygen, and the spin density attributed to a bivalent cobalt ion and a tetravalent cobalt ion is within a predetermined range. It is preferable that the positive electrode active material further contain magnesium. An appropriate magnesium concentration is represented as a concentration with respect to cobalt. It is also preferable that the positive electrode active material further contain fluorine.

公开(公告)号：US12142694B2

公开(公告)日：2024-11-12

申请号：US18208101

申请日：2023-06-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kenichi Okazaki ,  Masahiro Katayama ,  Masataka Nakada

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/146 ,  H01L29/49 ,  H10K59/121

Abstract: To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films.

公开(公告)号：US12142617B2

公开(公告)日：2024-11-12

申请号：US18232424

申请日：2023-08-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Hikaru Tamura

IPC: H01L27/146 ,  G09G3/36 ,  H01L29/786

Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.