公开(公告)号：US20240203785A1

公开(公告)日：2024-06-20

申请号：US18179377

申请日：2023-03-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Pin Hsu ,  Shih Hung Yang ,  Chu Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5283 ,  H01L29/0649

Abstract: A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

公开(公告)号：US12016250B2

公开(公告)日：2024-06-18

申请号：US17725511

申请日：2022-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

公开(公告)号：US12010931B2

公开(公告)日：2024-06-11

申请号：US17196979

申请日：2021-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.

公开(公告)号：US20240188278A1

公开(公告)日：2024-06-06

申请号：US18442116

申请日：2024-02-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yukihiro Nagai

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/50

Abstract: A method for forming a semiconductor structure for a memory device, including providing a substrate comprising a memory cell region and a peripheral circuit region defined thereon, and the peripheral circuit region comprising at least an active region formed therein, forming at least a buried gate structure in the active region, and an insulating layer being formed on a top of the buried gate structure, and forming a conductive line structure on the buried gate structure, and the conductive line structure and the buried gate structure being physically spaced apart and electrically isolated from each other by the insulating layer.

公开(公告)号：US12002681B2

公开(公告)日：2024-06-04

申请号：US17515541

申请日：2021-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/3086 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/3085 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

公开(公告)号：US11997935B2

公开(公告)日：2024-05-28

申请号：US17953341

申请日：2022-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/00

CPC classification number: H10N70/826 ,  H10N70/063 ,  H10N70/841 ,  H10N70/8833

Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.

公开(公告)号：US11990547B2

公开(公告)日：2024-05-21

申请号：US17033897

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yu Chen ,  Bo-Lin Huang ,  Jhong-Yi Huang ,  Keng-Jen Lin ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L29/16

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

公开(公告)号：US11990546B2

公开(公告)日：2024-05-21

申请号：US18120995

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

公开(公告)号：US11990346B2

公开(公告)日：2024-05-21

申请号：US17391075

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L21/311 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/32134 ,  H01L29/66545

Abstract: A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.

公开(公告)号：US20240162208A1

公开(公告)日：2024-05-16

申请号：US18077192

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L25/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/18 ,  H03H3/08 ,  H03H9/02

CPC classification number: H01L25/167 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786 ,  H01L31/022408 ,  H01L31/03044 ,  H01L31/035236 ,  H01L31/1856 ,  H03H3/08 ,  H03H9/02976

Abstract: A structure with a photodiode, an HEMT and an SAW device includes a photodiode and an HEMT. The photodiode includes a first electrode and a second electrode. The first electrode contacts a P-type III-V semiconductor layer. The second electrode contacts an N-type III-V semiconductor layer. The HEMT includes a P-type gate disposed on an active layer. A gate electrode is disposed on the P-type gate. Two source/drain electrodes are respectively disposed at two sides of the P-type gate. Schottky contact is between the first electrode and the P-type III-V semiconductor layer, and between the gate electrode and the P-type gate. Ohmic contact is between the second electrode and the first N-type III-V semiconductor layer, and between one of the two source/drain electrodes and the active layer and between the other one of two source/drain electrodes and the active layer.