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    METHOD FOR FORMING FIELD EFFECT TRANSISTORS
    132.
    发明申请
    METHOD FOR FORMING FIELD EFFECT TRANSISTORS 有权
    形成场效应晶体管的方法

    公开(公告)号：US20170040224A1

    公开(公告)日：2017-02-09

    申请号：US15252586

    申请日：2016-08-31

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

    IPC: H01L21/8238 ,  H01L29/66

    CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

    Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

    Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

    Reduced trench profile for a gate
    133.
    发明授权
    Reduced trench profile for a gate 有权
    降低了门的沟槽轮廓

    公开(公告)号：US09564501B2

    公开(公告)日：2017-02-07

    申请号：US14581741

    申请日：2014-12-23

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

    CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

    Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

    Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。

    Dual liner silicide
    134.
    发明授权
    Dual liner silicide 有权
    双衬里硅化物

    公开(公告)号：US09564372B2

    公开(公告)日：2017-02-07

    申请号：US14740987

    申请日：2015-06-16

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

    Inventor： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC: H01L21/82 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417

    CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

    Abstract translation: 制造双硅化物器件的方法包括：生长用于N型器件的源极和漏极（S / D）区域，在栅极结构上形成保护层，并且在N型器件的S / D区域上生长S / D区域用于P型设备。 第一电介质层被共形沉积，部分被去除以暴露S / D区域。 用于P型器件的暴露的S / D区域被硅化以形成衬垫。 第二电介质层被共形沉积。 在第二电介质层上形成电介质填充物。 接触孔通过第二介电层打开，露出P型器件的衬垫，露出N型器件的保护层。 通过打开保护层来暴露N型器件的S / D区域。 暴露的与栅极结构相邻的S / D区域被硅化以形成用于N型器件的衬垫。 触点形成。

    Gate structure cut after formation of epitaxial active regions
    136.
    发明授权
    Gate structure cut after formation of epitaxial active regions 有权
    形成外延活性区后的门结构切割

    公开(公告)号：US09559009B2

    公开(公告)日：2017-01-31

    申请号：US14876212

    申请日：2015-10-06

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

    IPC: H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L29/66

    CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

    Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

    Abstract translation: 形成跨越多个半导体材料部分的栅极结构。 源极区域和漏极区域形成在多个半导体材料部分中，并且形成横向围绕栅极结构的栅极间隔物。 通过选择性外延工艺从源极和漏极区域形成外延有源区。 通过切割掩模和蚀刻将栅极结构和栅极间隔物的组装切成多个部分以形成多个栅极组件。 每个门组件包括栅极结构部分和由栅极结构部分横向隔开的两个分离的栅极间隔部分。 可以从栅极间隔物的侧壁的周围去除外延有源区的一部分，以防止外延有源区中的电短路。 可以使用电介质间隔物或电介质衬垫来限制形成金属半导体合金的区域。

    Methods of forming reduced resistance local interconnect structures and the resulting devices
    137.
    发明授权
    Methods of forming reduced resistance local interconnect structures and the resulting devices 有权
    形成降低的电阻局部互连结构和所得器件的方法

    公开(公告)号：US09553028B2

    公开(公告)日：2017-01-24

    申请号：US14219365

    申请日：2014-03-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/823475 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/088 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.

    Abstract translation: 一种方法包括在绝缘材料层内的第一和第二晶体管之上形成绝缘材料层，形成用于第一和第二晶体管中的每一个的一组初始器件级触点，其中每组初始器件级触点包括 多个源极/漏极触点和栅极接触，形成初始局部互连结构，其导电耦合到第一和第二晶体管中的每一个中的初始器件级触点之一，以及去除初始局部互连结构和部分， 但不是所有的第一和第二晶体管的初始器件级触点。 该方法还包括在凹入的器件级触点上方形成铜局部互连结构和铜帽。

    HYBRID FIN CUTTING PROCESSES FOR FINFET SEMICONDUCTOR DEVICES
    139.
    发明申请
    HYBRID FIN CUTTING PROCESSES FOR FINFET SEMICONDUCTOR DEVICES 有权
    FINFET半导体器件的混合切割工艺

    公开(公告)号：US20160351411A1

    公开(公告)日：2016-12-01

    申请号：US14726712

    申请日：2015-06-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle

    IPC: H01L21/306 ,  H01L21/311 ,  H01L21/308

    CPC classification number: H01L21/3086 ,  H01L21/3083

    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin-removal masking layer comprised of a plurality of line-type features, each of which is positioned above one of the fins, and a masking material positioned at least between adjacent features of the fin-removal masking layer and above portions of an insulating material in the trenches between the fins. The method also includes performing an anisotropic etching process through the fin-removal masking layer to remove the portions of the fins to be removed.

    Abstract translation: 本文公开的一种说明性方法除其他外包括形成由多个线型特征组成的鳍去除掩模层，每个线型特征位于其中一个翅片上方，并且掩蔽材料至少位于相邻特征之间 翅片去除掩模层和鳍片之间的沟槽中的绝缘材料的上述部分。 该方法还包括通过散热器去除掩模层进行各向异性蚀刻工艺，以除去待除去的散热片的部分。

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