公开(公告)号：US20160268378A1

公开(公告)日：2016-09-15

申请号：US14645477

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/18 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/161

Abstract: A relaxed fin and a strained fin are formed upon a semiconductor substrate. The strained fin is more highly strained relative to relaxed fin. In a particular example, the relaxed fin may be SiGe (e.g., between 20% atomic Ge concentration and 40% atomic Ge concentration, etc.) and strained fin may be SiGe (e.g., between 50% atomic Ge concentration and 80% atomic Ge concentration, etc.). The strained fin may be located in a pFET region and the relaxed fin may be located in an nFET region of a semiconductor device. As such, mobility benefits may be achieved with the strained fin in the pFET region whilst mobility liabilities may be limited with the relaxed fin in nFET region. The height of the strained fin is greater relative to a critical thickness that which growth defects occur in an epitaxially formed Si blanket layer or in an epitaxially formed Ge blanket layer.

Abstract translation: 在半导体基板上形成松弛的翅片和应变翅片。 相对于松散的翅片，应变翅片更加紧张。 在特定的例子中，松散翅片可以是SiGe（例如，在20％的原子Ge浓度和40％的原子Ge浓度之间等等），并且应变翅片可以是SiGe（例如，在50％的原子Ge浓度和80％的原子Ge之间 浓度等）。 应变鳍片可以位于pFET区域中，并且松弛鳍片可以位于半导体器件的nFET区域中。 因此，可以通过pFET区域中的应变鳍实现移动性益处，而移动性负载可以由nFET区域中的松散鳍限制。 应变翅片的高度相对于在外延形成的Si覆盖层中或在外延形成的Ge覆盖层中发生生长缺陷的临界厚度更大。

公开(公告)号：US09390939B2

公开(公告)日：2016-07-12

申请号：US14289737

申请日：2014-05-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/51 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material.

Abstract translation: 所公开的一种方法包括在接触开口中顺应地沉积接触绝缘材料层和导电材料层，在接触开口中形成减小厚度的牺牲材料层，以暴露部分，但不是全部， 的导电材料层的去除部分，去除部分导电材料层和接触绝缘材料层位于减薄厚度的牺牲材料层的上表面之上，去除减薄的牺牲材料层，并在其中形成导电接触 接触开口，其接触导电材料层的凹部和接触绝缘材料层。

公开(公告)号：US09390925B1

公开(公告)日：2016-07-12

申请号：US14572975

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/00 ,  H01L21/225 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161

Abstract: Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.

Abstract translation: 通过以下步骤构造SiGe翅片：（i）提供包括从基底层向上方延伸的含硅基底层和含硅的第一翅片结构的中间子组件; （ii）通过用包括硅的预热氧化层覆盖基层的顶表面的至少一部分和第一鳍结构的第一和第二侧表面的至少一部分来精炼子组件 锗（SiGe）; 和（iii）通过热氧化预热氧化层以使Ge含量从预热氧化层迁移到基层的至少一部分和第一翅片结构的至少一部分中，进一步细化子组件。

公开(公告)号：US09385231B2

公开(公告)日：2016-07-05

申请号：US14530796

申请日：2014-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/04 ,  H01L29/08 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78654

Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.

Abstract translation: 包括外延源极和漏极区域的FET结构包括大的接触区域，并且具有低电阻率和低的寄生栅极至源极/漏极电容。 源极和漏极区域被横向蚀刻以提供用于容纳低k电介质材料的凹部，而不损害源极/漏极区域及其相关联的接触之间的接触面积。 高K电介质层设置在凸起的源极/漏极区域和栅极导体之间​​以及栅极导体和诸如ETSOI或PDSOI衬底之类的衬底之间。 该结构可用于诸如MOSFET器件的电子器件中。

公开(公告)号：US09378948B2

公开(公告)日：2016-06-28

申请号：US14672157

申请日：2015-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L21/02532 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.

公开(公告)号：US09373637B2

公开(公告)日：2016-06-21

申请号：US14526767

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L27/06 ,  H01L29/06 ,  H01L29/36 ,  H01L29/417 ,  H01L49/02 ,  H01L21/84 ,  H01L27/13

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/13 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/41783

Abstract: An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.

公开(公告)号：US20160141368A1

公开(公告)日：2016-05-19

申请号：US14540051

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic Schepis

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/02123 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming one or more tall strained silicon germanium (SiGe) fins on a semiconductor on insulator (SOI) substrate. The fins have a germanium (Ge) concentration which may differ from the Ge concentration within the top layer of the SOI substrate. The difference in Ge concentration between the fins and the top layer of the SOI substrate may range from approximately 10 atomic percent to approximately 40 atomic percent. This Ge concentration differential may be used to tailor a strain on the fins. The strain on the fins may be tailored to increase the critical thickness and allow for a greater height of the fins as compared to conventional strained fins of the same SiGe concentration formed from bulk material.

Abstract translation: 本发明一般涉及半导体器件，更具体地，涉及在绝缘体上半导体（SOI）衬底上形成一个或多个高应变硅锗（SiGe）鳍片的结构和方法。 散热片的锗（Ge）浓度可能与SOI衬底的顶层内的Ge浓度不同。 SOI衬底的翅片和顶层之间的Ge浓度的差可以在约10原子％至约40原子％的范围内。 该Ge浓度差可用于调节鳍片上的应变。 与散装材料形成的相同SiGe浓度的常规应变翅片相比，翅片上的应变可以被调整以增加临界厚度并允许翅片更大的高度。

公开(公告)号：US09343550B2

公开(公告)日：2016-05-17

申请号：US14666469

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by removing a sacrificial portion formed between the substrate and the active fin. The sacrificial portion may be doped to allow for a greater thickness relative to an un-doped portion of substantially similar composition. The doped sacrificial portion thickness may be between 10 nm and 250 nm. The thicker sacrificial portion allows for a thicker insulator so as to provide adequate electrical isolation between the active fin and the substrate. During formation of the void, the active fin may be supported by a gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the sacrificial portion material.

Abstract translation: 半导体器件包括形成在空隙内的绝缘体，以将活性鳍与下面的衬底电隔离。 通过去除形成在衬底和活性鳍片之间的牺牲部分来产生空隙。 牺牲部分可以被掺杂以允许相对于基本相似组成的未掺杂部分具有更大的厚度。 掺杂的牺牲部分厚度可以在10nm和250nm之间。 较厚的牺牲部分允许较厚的绝缘体，以便在活性鳍片和衬底之间提供足够的电绝缘。 在形成空隙期间，活性翅片可以由浇口支撑。 半导体结构还可以包括具有牺牲部分材料的至少保持部分的主体区域。

公开(公告)号：US09324870B2

公开(公告)日：2016-04-26

申请号：US14020923

申请日：2013-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1211 ,  H01L29/32 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

Abstract translation: 通过控制半导体鳍片的表面上沉积的半导体材料的生长速率，可以在同一衬底上同时形成半导体鳍片上的合并和未熔合的凸起的有源区域。 在一个实施例中，生长速率缓冲掺杂剂可以通过成角度的离子注入注入第一半导体鳍片的侧壁表面上，在第二半导体鳍片被掩模层掩蔽的同时，其中需要延长生长速率。 在另一个实施例中，通过离子注入可以将生长速率增强掺杂剂注入到第二半导体鳍片的侧壁表面上，而第一半导体鳍片被掩蔽层掩蔽。 沉积的半导体材料的不同的生长速率可以使得第一半导体散热片上的凸起的有源区域保持不熔化，并且使第二半导体鳍片上的有源区域升高以合并。

公开(公告)号：US09318580B2

公开(公告)日：2016-04-19

申请号：US14590327

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02494 ,  H01L21/02587 ,  H01L29/7853

Abstract: A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are formed in a crystalline layer. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. Backfilling is formed underneath the U-shaped semiconductor material with a dielectric material for support. A semiconductor device is formed with the U-shaped semiconductor material.

Abstract translation: 形成U型半导体器件的方法包括沿形成在晶体层中的沟槽的侧壁和底部生长U形半导体材料。 U型半导体材料被锚固，并且去除晶体层。 在具有用于支撑的电介质材料的U形半导体材料下形成回填。 半导体器件由U形半导体材料形成。