公开(公告)号：US20170365681A1

公开(公告)日：2017-12-21

申请号：US15679077

申请日：2017-08-16

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew METZ ,  Jack T. KAVALIEROS ,  Nancy M. ZELICK ,  Robert S. CHAU

IPC: H01L29/51 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/49 ,  H01L23/485 ,  H01L29/78 ,  H01L45/00 ,  H01L33/40 ,  H01L33/00 ,  H01L31/0224 ,  H01L29/45 ,  H01L21/04 ,  H01L51/10 ,  H01L51/44 ,  H01L51/52 ,  H01B1/12

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

公开(公告)号：US20170317172A1

公开(公告)日：2017-11-02

申请号：US15650569

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Jack T. KAVALIEROS ,  Nancy ZELICK ,  Been-Yih JIN ,  Markus KUHN ,  Stephen M. CEA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

公开(公告)号：US20170263706A1

公开(公告)日：2017-09-14

申请号：US15529481

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia M. RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

公开(公告)号：US20170012125A1

公开(公告)日：2017-01-12

申请号：US15119345

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Robert S. CHAU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述用于制造垂直半导体器件和纵向半导体器件的纵横比捕获（ART）方法。 例如，半导体器件包括具有第一晶格常数的最上表面的衬底。 第一源极/漏极区域设置在衬底的最上表面上并且具有第二不同的晶格常数。 垂直沟道区域设置在第一源极/漏极区域上。 第二源极/漏极区域设置在垂直沟道区域上。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20160372597A1

公开(公告)日：2016-12-22

申请号：US15250836

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Titash RAKSHIT ,  Martin GILES ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/7845 ,  H01L21/8234 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

公开(公告)号：US20160211263A1

公开(公告)日：2016-07-21

申请号：US14915185

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niti GOEL ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

Abstract translation: 从形成在浅沟槽隔离（STI）区域之间的一个或一对沟槽的底部的衬底表面外延生长单个鳍或一对共同组合的n型和p型单晶电子器件鳍。 翅片或翅片被图案化并且STI区域被蚀刻以形成在STI区域的蚀刻顶表面之上延伸的翅片或翅片的高度。 翅片高度可以是其宽度的至少1.5倍。 暴露的侧壁表面和每个翅片的顶表面用一个或多个共形外延材料外延包层以在翅片上形成器件层。 在生长翅片之前，可以从衬底表面生长毯式缓冲外延材料; 并且生长在STI沟槽中的翅片形成在覆盖层上方。 翅片的这种形成减少了材料界面晶格失配的缺陷。

公开(公告)号：US20160204263A1

公开(公告)日：2016-07-14

申请号：US14914906

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ravi PILLARISETTY ,  Niti GOEL ,  Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

Abstract translation: 一种包括半导体本体的装置，包括沟道区和设置在沟道区的相对侧上的结区，所述半导体本体包括包括第一带隙的第一材料; 以及包括第二材料的多个纳米线，所述第二材料包括不同于所述第一带隙的第二带隙，所述多个纳米线设置在穿过所述第一材料的分开的平面中，使得所述第一材料围绕所述多个纳米线中的每一个; 以及设置在通道区域上的栅极堆叠。 一种方法，包括在衬底上方的分开的平面中形成多个纳米线，所述多个纳米线中的每一个包括包括第一带隙的材料; 在所述多个纳米线的每一个周围分别形成包层材料，所述包层材料包括第二带隙; 聚结包层材料; 并在所述包层材料上设置栅极叠层。

公开(公告)号：US20160204208A1

公开(公告)日：2016-07-14

申请号：US14778574

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Niti GOEL ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/0607 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract translation: 第一种基于III-V材料的缓冲层沉积在硅衬底上。 第二个III-V材料的缓冲层沉积在第一个III-V材料的缓冲层上。 在基于第二III-V材料的缓冲层上沉积基于III-V材料的器件沟道层。