公开(公告)号：US20240224508A1

公开(公告)日：2024-07-04

申请号：US18090816

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Pushkar RANADE ,  Sagar SUTHRAM

IPC: H10B12/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B12/36 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/7851 ,  H01L29/78696

Abstract: Structures having bit-cost scaling with relaxed transistor area are described. In an example, an integrated circuit structure includes a plurality of plate lines along a first direction. A transistor is beneath the plurality of plate lines, with a direction of a first source or drain to a gate to a second source or drain of the transistor being a second direction orthogonal to the first direction. A plurality of capacitor structures is over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines. The plurality of capacitor structures has a staggered arrangement from a plan view perspective.

公开(公告)号：US20240224488A1

公开(公告)日：2024-07-04

申请号：US18089865

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H10B10/00 ,  H01L23/48 ,  H01L25/065 ,  H10B12/00

CPC classification number: H10B10/125 ,  H01L23/481 ,  H01L25/0657 ,  H10B12/056

Abstract: Structures having two-level memory are described. In an example, an integrated circuit structure includes an SRAM layer including transistors. A DRAM layer is vertically spaced apart from the transistors of the SRAM layer. A metallization structure is between the transistors of the SRAM layer and the DRAM layer.

公开(公告)号：US20240222438A1

公开(公告)日：2024-07-04

申请号：US18089945

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/26 ,  H01L29/36 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/26 ,  H01L29/36 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7787

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for designing and fabricating semiconductor packages that include transistors that include wide band gap materials, such as silicon carbide or gallium nitride. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222435A1

公开(公告)日：2024-07-04

申请号：US18089936

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Han Wui THEN ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/105

CPC classification number: H01L29/1608 ,  H01L21/02447 ,  H01L21/02529 ,  H01L27/105

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.

公开(公告)号：US20240215256A1

公开(公告)日：2024-06-27

申请号：US18088552

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Pushkar RANADE ,  Sagar SUTHRAM

IPC: H10B53/20 ,  H01L23/522 ,  H01L23/528 ,  H10B53/10 ,  H10B61/00

CPC classification number: H10B53/20 ,  H01L23/5226 ,  H01L23/5283 ,  H10B53/10 ,  H10B61/10 ,  H10B61/22

Abstract: Structures having backside capacitors are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of select transistors, a plurality of metallization layers above the plurality of select transistors, and a plurality of vias below and coupled to the plurality of select transistors. A backside structure is below the plurality of vias of the device layer. The backside structure includes a memory layer coupled to the plurality of select transistors by the plurality of vias.

公开(公告)号：US20240215222A1

公开(公告)日：2024-06-27

申请号：US18088543

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Sagar SUTHRAM ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: Structures having backside power delivery and signal routing for front side DRAM are described. In an example, an integrated circuit structure includes a front side structure including a dynamic random access memory (DRAM) layer having one or more capacitors over one or more transistors, and a plurality of metallization layers above the DRAM layer. A backside structure is below and coupled to the transistors of the DRAM layer, the backside structure including metal lines for power delivery and signal routing to the one or more transistors of the DRAM layer.

公开(公告)号：US20240164080A1

公开(公告)日：2024-05-16

申请号：US18375858

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Peng ZHENG ,  Varun MISHRA ,  Harold W. KENNEL ,  Eric A. KARL ,  Tahir GHANI

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/10

CPC classification number: H10B10/12 ,  H01L29/0669 ,  H01L29/1037

Abstract: Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.

公开(公告)号：US20240153956A1

公开(公告)日：2024-05-09

申请号：US18409519

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20240113161A1

公开(公告)日：2024-04-04

申请号：US18540544

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Nicholas G. MINUTILLO ,  Sean T. MA ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/785

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20240113109A1

公开(公告)日：2024-04-04

申请号：US17958291

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Robert JOACHIM ,  Shengsi LIU ,  Hongqian SUN ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/00

CPC classification number: H01L27/088 ,  H01L21/8234 ,  H01L23/564

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug between two gates within a transistor layer of a semiconductor device. In embodiments, the plug includes a cap at a top of the plug and a liner surrounding at least a portion of the cap, and a base below the cap and the liner. The cap may include a metal. A top of the cap may be even with, or substantially even with, the top of the two gates. The plug may provide a more even surface at a top of a transistor layer where the plug fills in for a gate cut. Other embodiments may be described and/or claimed.