公开(公告)号：US09466673B2

公开(公告)日：2016-10-11

申请号：US15076871

申请日：2016-03-22

Applicant: International Business Machines Corporation

Inventor： Gen P. Lauer ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L21/00 ,  H01L29/10 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/02 ,  H01L21/324 ,  H01L21/3065

CPC classification number: H01L29/1054 ,  G05B19/19 ,  G05B2219/45032 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/7849 ,  H01L29/785

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

公开(公告)号：US20160284604A1

公开(公告)日：2016-09-29

申请号：US14671041

申请日：2015-03-27

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/42388

Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

Abstract translation: 在一个方面，形成CMOS器件的方法包括形成悬挂在BOX上的纳米线，其中第一/第二个或多个纳米线在BOX上的第一/第二悬架高度处悬挂，并且其中第一悬浮高度为 大于第二悬架高度; 在BOX上并围绕纳米线沉积共形栅极电介质，其中沉积在BOX上的共形栅极电介质是i）与保形栅极电介质沉积在第一个或多个纳米线周围的非接触位置，以及ii）是 与围绕第二个或多个纳米线沉积的共形栅极电介质直接物理接触，使得BOX在保形氧化物层在共形栅极电介质和第二个或多个之间的界面处生长期间用作氧源 纳米线。

公开(公告)号：US20160211327A1

公开(公告)日：2016-07-21

申请号：US15076871

申请日：2016-03-22

Applicant: International Business Machines Corporation

Inventor： Gen P. Lauer ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L29/10 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/324 ,  H01L21/84 ,  H01L29/161

CPC classification number: H01L29/1054 ,  G05B19/19 ,  G05B2219/45032 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/7849 ,  H01L29/785

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

公开(公告)号：US20160196867A1

公开(公告)日：2016-07-07

申请号：US14589075

申请日：2015-01-05

Applicant: International Business Machines Corporation

Inventor： Leland Chang ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/7391

Abstract: In some embodiments, an apparatus for storing data includes a state retention circuit configured to retain a first state when placed into the first state and a second state when placed into the second state, a write port operably connected to the state retention circuit and configured to receive a data input and place the state retention circuit into a written state corresponding to the data input, a read port operably connected to the state retention circuit and configured to drive a data output according to the written state. In one embodiment, the write port and the read port comprise CMOS transistors and no tunneling field effect transistors, and the state retention circuit comprises tunneling field effect transistors and no CMOS transistors. A corresponding system and computer readable medium are also disclosed herein.

Abstract translation: 在一些实施例中，一种用于存储数据的装置包括状态保持电路，其被配置为在放置到第一状态时保持第一状态，而当被置于第二状态时保持第二状态;写入端口，可操作地连接到状态保持电路并且被配置为 接收数据输入并将状态保持电路置于对应于数据输入的写入状态，读端口可操作地连接到状态保持电路并且被配置为根据写入状态驱动数据输出。 在一个实施例中，写入端口和读取端口包括CMOS晶体管和无隧道场效应晶体管，并且状态保持电路包括隧道场效应晶体管和无CMOS晶体管。 本文还公开了相应的系统和计算机可读介质。

公开(公告)号：US20160181277A1

公开(公告)日：2016-06-23

申请号：US15057900

申请日：2016-03-01

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/78696

Abstract: In one aspect, a method of forming a multiple VT device structure includes the steps of: forming an alternating series of channel and barrier layers as a stack having at least one first channel layer, at least one first barrier layer, and at least one second channel layer; defining at least one first and at least one second active area in the stack; selectively removing the at least one first channel/barrier layers from the at least one second active area, such that the at least one first channel layer and the at least one second channel layer are the top-most layers in the stack in the at least one first and the at least one second active areas, respectively, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area.

Abstract translation: 一方面，一种形成多个VT器件结构的方法包括以下步骤：形成交替的沟道和阻挡层系列作为具有至少一个第一沟道层，至少一个第一势垒层和至少一个第二栅极层 通道层; 限定所述堆叠中的至少一个第一和至少一个第二有效区域; 选择性地从所述至少一个第二有源区域去除所述至少一个第一沟道/势垒层，使得所述至少一个第一沟道层和所述至少一个第二沟道层至少在所述堆叠中的最顶层 一个第一和至少一个第二有源区，其中至少一个第一势垒层被配置为将电荷载流子限制在第一有源区中的至少一个第一沟道层。

公开(公告)号：US09373638B1

公开(公告)日：2016-06-21

申请号：US14597918

申请日：2015-01-15

Applicant: International Business Machines Corporation

Inventor： Gen P. Lauer ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  G05B19/19

CPC classification number: H01L29/1054 ,  G05B19/19 ,  G05B2219/45032 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/7849 ,  H01L29/785

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

Abstract translation: 访问具有nFET和pFET区域的硅锗绝缘体（SGOI）晶片，SGOI晶片具有具有第一锗（Ge）浓度的硅锗（SiGe）层，以及nFET和pFET上的第一氧化物层，并且去除第一 pFET上的氧化层。 然后，将pFET中的SiGe层中的第一Ge浓度提高到第二Ge浓度，并且去除nFET上的第一氧化物层。 然后，使nFET中的第一Ge浓度的SiGe层凹陷，使得SiGe层与第二Ge浓度的pFET中的SiGe层成平面。 然后，在nFET中的SGOI上生长硅（Si）层，并且在pFET中生长第三浓度的SiGe层，其中第三浓度的SiGe层与生长的nFET Si层成平面。

公开(公告)号：US09324801B2

公开(公告)日：2016-04-26

申请号：US14511837

申请日：2014-10-10

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L29/06 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.

Abstract translation: 在基板的表面上形成包括硅锗合金部和硅部的散热片。 牺牲栅结构然后形成跨越每个鳍堆叠。 暴露的硅锗合金部分被氧化，而被牺牲栅极结构覆盖的硅锗合金部分不被氧化。 形成具有与每个牺牲栅极结构的最顶表面共面的最顶表面的电介质材料，然后除去每个牺牲栅极结构。 去除非氧化硅锗合金部分，悬浮在每个未氧化的硅锗合金部分上存在的硅部分。 然后在每个悬置的硅部分周围形成功能门结构。 氧化硅锗合金部分保留并向悬浮硅部分的通道部分提供应力。

公开(公告)号：US09209095B2

公开(公告)日：2015-12-08

申请号：US14245683

申请日：2014-04-04

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/24 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L29/735 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0257 ,  H01L21/02595 ,  H01L21/225 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/244 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/06 ,  H01L29/0673 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/6625 ,  H01L29/6631 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/735 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/78696

Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. Fin hardmasks are formed on the wafer. A dummy gate is formed on the wafer, over the fin hardmasks. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer and the dummy gate is removed selective to the dielectric filler layer so as to form a trench in the filler layer. Fins are patterned in the wafer using the fin hardmasks exposed within the trench, wherein the fins will serve as a base region of the bipolar transistor device. The fins are recessed in the base region. The base region is re-grown from an epitaxial SiGe, Ge or III-V semiconductor material. A contact is formed to the base region.

Abstract translation: 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 翅片硬掩模形成在晶片上。 在晶片上，在翅片硬掩模上形成虚拟栅极。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 将介电填料层沉积在晶片上，并且将虚拟栅极选择性地去除介电填料层，以便在填料层中形成沟槽。 使用暴露在沟槽内的散热片硬掩模，在晶片中图案化鳍片，其中鳍片将用作双极晶体管器件的基极区域。 翅片凹入基部区域。 从外延SiGe，Ge或III-V半导体材料再生长基极区。 在基部区域形成接触。

公开(公告)号：US09105650B2

公开(公告)日：2015-08-11

申请号：US14186512

申请日：2014-02-21

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Gen Pei Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L29/73 ,  H01L21/84

CPC classification number: H01L29/66265 ,  H01L21/84 ,  H01L29/6625 ,  H01L29/7317

Abstract: A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.

Abstract translation: 一种形成横向双极晶体管的方法包括：形成具有底部衬底层的绝缘体上硅（SOI）衬底，在衬底层顶部的掩埋氧化物层（BOX）和绝缘体上硅绝缘体（SOI）层上的绝缘体上硅 BOX层，在绝缘体上硅层顶部形成一个虚拟栅极和间隔物，用正离子或负离子掺杂SOI层，使用化学机械平面化（CMP）沉积层间电介质（ILD）来平坦化ILD， 去除虚拟栅极，产生显示虚拟栅极的基极的栅极沟槽，掺杂伪栅极基底，在SOI层的顶部上沉积多晶硅层并进入栅极沟槽，蚀刻多晶硅层，使得其仅覆盖 虚拟栅极基极，以及施加自对准硅化物工艺。

公开(公告)号：US20150048428A1

公开(公告)日：2015-02-19

申请号：US13966885

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Jack Oon Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02647 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.