公开(公告)号：US11764306B2

公开(公告)日：2023-09-19

申请号：US17472879

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Gilbert Dewey ,  Kent Millard ,  Jack Kavalieros ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Justin R. Weber ,  Tahir Ghani ,  Li Huey Tan ,  Kevin Lin

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/78693 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/267

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

公开(公告)号：US11756998B2

公开(公告)日：2023-09-12

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0684 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20230282717A1

公开(公告)日：2023-09-07

申请号：US17687032

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Nikhil J. Mehta ,  Krishna Ganesan ,  Chanaka D. Munasinghe ,  Tahir Ghani ,  Charles H. Wallace

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/401

Abstract: Techniques are provided herein to form semiconductor devices that use uniform topside dielectric plugs as masking structures to form conductive contacts to various source or drain regions. In an example, a plurality of semiconductor devices each include one or more semiconductor regions extending in a first direction between corresponding source or drain regions. The source or drain regions are adjacent to one another along a second direction different from the first direction. Conductive contacts are formed over the source or drain regions of the semiconductor devices. A dielectric fill is between one or more adjacent pairs of conductive contacts and dielectric masking structures having a substantially uniform thickness are present over the dielectric fill between adjacent pairs of conductive contacts. This uniform thickness characteristic applies to all of the masking structures regardless of their length along the second direction.

公开(公告)号：US20230282574A1

公开(公告)日：2023-09-07

申请号：US17685539

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Tahir Ghani ,  Charles H. Wallace ,  Desalegne B. Teweldebrhan

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76837 ,  H01L23/5226

Abstract: An integrated circuit device includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes (i) a first dielectric material, (ii) a recess within the first dielectric material, and (iii) a first interconnect feature within the recess. In an example, a top surface of the first interconnect feature is at least 1 nanometer (nm), or at least 3 nm, or at least 5 nm below a top surface of the first dielectric material. The second interconnect layer includes (i) a second dielectric material, and (ii) a second interconnect feature within the second dielectric material. In an example, the second interconnect feature is at least in part above, and conductively coupled to, the first interconnect feature. In an example, a bottom section of the second interconnect feature is within a top section of the recess.

公开(公告)号：US20230275067A1

公开(公告)日：2023-08-31

申请号：US17680368

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/38 ,  H01L23/473

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L23/38 ,  H01L23/473 ,  H01L2225/06589

Abstract: Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

公开(公告)号：US20230268410A1

公开(公告)日：2023-08-24

申请号：US17677909

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/04 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78696

Abstract: IC devices including vertical TFETs are disclosed. An example IC device includes a substrate, a channel region, a first region, and a second region. One of the first and second regions is a source region and another one is a drain region. The first region includes a first semiconductor material. The second region includes a second semiconductor material that may be different from the first semiconductor material. The first region and the second region are doped with opposite types of dopants. The channel region includes a third semiconductor material that may be different from the first or second semiconductor material. The channel region is between the first region and the second region. The first region is between the channel region and the substrate. In some embodiments, the first or second region is formed through layer transfer or epitaxy (e.g., graphoepitaxy, chemical epitaxy, or a combination of both).

公开(公告)号：US20230268392A1

公开(公告)日：2023-08-24

申请号：US17678928

申请日：2022-02-23

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0669 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/78618 ,  H01L29/66742 ,  H01L27/0886

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Embodiments of the present disclosure are based on recognition that extending at least one of two S/D contacts of a transistor into a channel layer while keeping it separated from a corresponding gate stack by a channel material may allow keeping the footprint of the transistor relatively small while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower. For multiple transistors, some of the S/D contacts may be shared to further increase transistor density.

公开(公告)号：US11715787B2

公开(公告)日：2023-08-01

申请号：US17514058

申请日：2021-10-29

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/266 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7853

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

公开(公告)号：US11699756B2

公开(公告)日：2023-07-11

申请号：US17541199

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7846 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/42364

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US20230207560A1

公开(公告)日：2023-06-29

申请号：US17561244

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Nicholas Minutillo ,  Ryan Cory Haislmaier ,  Yulia Tolstova ,  Yoon Jung Chang ,  Tahir Ghani ,  Szuya S. Liao ,  Anand Murthy ,  Pratik Patel

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823412

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device on a substrate comprising: a gate structure including a metal, the gate structure on a channel structure; a source structure in a first trench at a first side of the gate structure; a drain structure in a second trench at a second side of the gate structure; a capping layer on individual ones of the source structure and of the drain structure. The capping layer comprising a semiconductor material of a same group as a semiconductor material of a corresponding one of the source structure or of the drain structure, wherein an isotope of a p-type dopant in the capping layer represents an atomic percentage of at least about 95% of a p-type isotope content of the capping layer; and metal contact structures coupled to respective ones of the source structure and of the drain structure.