公开(公告)号：US20180323144A1

公开(公告)日：2018-11-08

申请号：US15584881

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5227 ,  H01L23/481

Abstract: A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed around the first TSV. The second die includes a second TSV coupled to the first TSV and a second substantially helical conductor disposed around the second TSV. The first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.

公开(公告)号：US09935085B2

公开(公告)日：2018-04-03

申请号：US15361659

申请日：2016-11-28

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative system in accordance with a particular embodiment includes a semiconductor substrate having an opening that includes a generally cylindrical portion with a generally smooth, uniform surface. The opening also includes a terminal portion extending transversely to the cylindrical portion and intersecting. A single, uniform, homogeneous volume of conductive material is disposed in both the cylindrical portion and the terminal portion of the opening, the conductive material forming a conductive path in the cylindrical portion and at least a portion of a conductive terminal in the terminal portion. The conductive terminal has a cross-section with generally flat walls aligned with crystal planes of the semiconductor substrate material. The conductive terminal projects away from the semiconductor substrate.

公开(公告)号：US09343368B2

公开(公告)日：2016-05-17

申请号：US14324958

申请日：2014-07-07

Applicant: Micron Technology, Inc. ,  Russell D. Slifer

Inventor： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/82 ,  H01L23/525 ,  H01L23/60 ,  H01L25/065 ,  H01L25/00 ,  H01L21/50 ,  H01L23/52 ,  H01L23/62

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

公开(公告)号：US09343362B2

公开(公告)日：2016-05-17

申请号：US14144806

申请日：2013-12-31

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC: H01L21/02 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

Abstract translation: 具有通硅通孔的微电子器件及其相关制造方法。 一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。 该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

公开(公告)号：US20160086926A1

公开(公告)日：2016-03-24

申请号：US14959500

申请日：2015-12-04

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt ,  Kyle K. Kirby ,  Dewali Ray

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/043 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/00014

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

Abstract translation: 本文公开了用于微电子管芯的直通互连结构以及相关联的系统和方法。 在一个实施例中，微电子管芯组件包括支撑衬底，至少部分地位于支撑衬底上方的第一微电子管芯，以及至少部分地位于第一管芯上方的第二微电子管芯。 所述第一裸片包括半导体衬底，在所述半导体衬底的一部分上延伸的导电迹线，所述迹线与所述半导体衬底的所述部分之间的衬底焊盘以及穿过所述迹线的穿硅通孔（TSV），所述衬底 衬垫和半导体衬底的部分。 第二管芯经由包括TSV的导电路径电耦合到支撑衬底。

公开(公告)号：US20150303095A1

公开(公告)日：2015-10-22

申请号：US14755274

申请日：2015-06-30

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/265 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20140284796A1

公开(公告)日：2014-09-25

申请号：US14300004

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Kyle K. Kirby

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.

Abstract translation: 本文公开了用于在微特征工件和模具中填充通孔并形成导电互连的微电子器件和方法。 在一个实施例中，一种方法包括提供具有多个模具的微特征工件和从微特征工件的第一侧延伸穿过微特征工件的至少一个通道到微特征工件的相对的第二侧。 该方法还可以包括在邻近微电子工件的第一侧的通道中形成导电插塞，以及在通道中沉积导电材料，以至少大体上填充从导电插头到微电子工件的第二侧的通道。

公开(公告)号：US12300570B2

公开(公告)日：2025-05-13

申请号：US17583038

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Kyle K. Kirby

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/603 ,  H01L23/31 ,  H01L23/544 ,  H01L25/16

Abstract: A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

公开(公告)号：US20240379568A1

公开(公告)日：2024-11-14

申请号：US18780253

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/538 ,  G11C5/02 ,  G11C5/06 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

公开(公告)号：US12074094B2

公开(公告)日：2024-08-27

申请号：US17670378

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2225/06541

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.