公开(公告)号：US20140179111A1

公开(公告)日：2014-06-26

申请号：US13791125

申请日：2013-03-08

Applicant: Applied Materials, Inc.

Inventor： Jie Liu ,  Jingchun Zhang ,  Anchuan Wang ,  Nitin K. Ingle ,  Seung Park ,  Zhijun Chen ,  Ching-Mei Hsu

IPC: H01L21/3065

CPC classification number: H01L21/32136 ,  H01J37/32357

Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.

Abstract translation: 描述了相对于图案化异质结构上的其它材料蚀刻暴露的氮化钛的方法，并且可以包括由含氟前体形成的远程等离子体蚀刻。 包括来自远程等离子体的等离子体流出物的前体组合流入基板处理区域以在各种操作条件下以高氮化钛选择性蚀刻图案化结构。 该方法可用于以比各种金属，氮化物和氧化物化合物更快的速率除去氮化钛。

公开(公告)号：US08541312B2

公开(公告)日：2013-09-24

申请号：US13745109

申请日：2013-01-18

Applicant: Applied Materials, Inc.

Inventor： Yunyu Wang ,  Anchuan Wang ,  Jingchun Zhang ,  Nitin K. Ingle ,  Young S. Lee

IPC: H01L21/302 ,  B44C1/22

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J37/32449 ,  H01L21/32137

Abstract: A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch selectivity of silicon relative to silicon nitride and other silicon-and-nitrogen-containing material is increased using the method. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-nitrogen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including nitrogen trifluoride and hydrogen (H2). The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.

Abstract translation: 描述了抑制图案化异质结构上暴露的含硅和氮的材料的蚀刻速率的方法，并且包括两级远程等离子体蚀刻。 使用该方法，硅相对于氮化硅和其它含硅和氮的材料的蚀刻选择性增加。 远程等离子体蚀刻的第一阶段使等离子体流出物与图案化的异质结构反应，以在含硅和氮的材料上形成保护性固体副产物。 第一级的等离子体流出物由包括三氟化氮和氢气（H 2）在内的前体组合的远程等离子体形成。 远程等离子体蚀刻的第二阶段还使等离子体流出物与图案化的异质结构反应，以选择性地去除缺乏保护性固体副产物的材料。 第二级的等离子体流出物由含氟前体的远程等离子体形成。

公开(公告)号：US20250066913A1

公开(公告)日：2025-02-27

申请号：US18455508

申请日：2023-08-24

Applicant: Applied Materials, Inc.

Inventor： Supriya Ghosh ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  Nitin K. Ingle ,  Diwakar Kedlaya ,  Priya Chouhan

IPC: C23C16/455 ,  C23C16/40 ,  H01J37/32 ,  H01L21/02

Abstract: Methods of filling a feature on a semiconductor substrate may include performing a process to fill the feature on the semiconductor substrate by repeatedly performing first operations. First operations can include providing a silicon-containing precursor. First operations can include contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the feature defined on the substrate. First operations can include purging the semiconductor processing chamber. First operations can include providing an oxygen-and-hydrogen-containing precursor. First operations can include contacting the substrate with the oxygen-and-hydrogen-containing precursor to form a silicon-and-oxygen-containing material within the feature defined on the substrate.

公开(公告)号：US20250029841A1

公开(公告)日：2025-01-23

申请号：US18223156

申请日：2023-07-18

Applicant: Applied Materials, Inc.

Inventor： Jiayin Huang ,  Zihui Li ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3065 ,  H01L21/02

Abstract: Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing region of a semiconductor processing chamber. A first layer of silicon-and-germanium-containing material and a second layer of silicon-and-germanium-containing material may be disposed on a substrate housed within the processing region. A native oxide may be present on the first layer and the second layer. The methods may include contacting the substrate with the pre-treatment precursor to remove the native oxide. The methods may include providing an oxygen-containing precursor to the processing region. The methods may include contacting the substrate with the oxygen-containing precursor to oxidize at least a portion of the second layer. The methods may include providing an etchant precursor to the processing region. The methods may include contacting the substrate with the etchant precursor to selectively etch the first layer of silicon-and-germanium-containing material.

公开(公告)号：US20240290623A1

公开(公告)日：2024-08-29

申请号：US18115269

申请日：2023-02-28

Applicant: Applied Materials, Inc.

Inventor： Bin Yao ,  Zihui Li ,  Jiayin Huang ,  Anchuan Wang ,  Chia-Ling Kao ,  Nitin K. Ingle

IPC: H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J37/32816 ,  H01J2237/182 ,  H01J2237/334

Abstract: Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the pre-treatment precursor in the remote plasma system. The methods may include flowing plasma effluents of the pre-treatment precursor to a processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be disposed within the processing region. The alternating layers of material may include a silicon-and-germanium-containing material. The methods may include contacting the substrate with the plasma effluents of the pre-treatment precursor. The methods may include etching the silicon-and-germanium-containing material. The methods may include providing a post-treatment precursor to the processing region. The methods may include contacting the substrate with the post-treatment precursor. The methods may include removing the portion of the silicon-and-germanium-containing material.

公开(公告)号：US20240087910A1

公开(公告)日：2024-03-14

申请号：US17944540

申请日：2022-09-14

Applicant: Applied Materials, Inc.

Inventor： Lala Zhu ,  Shi Che ,  Dongqing Yang ,  Nitin K. Ingle

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/31116 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/324

Abstract: A semiconductor processing method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include an exposed region of silicon-and-oxygen-containing material. The substrate may include an exposed region of a liner material. The methods may include providing a hydrogen-containing precursor to the semiconductor processing region. The methods may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The methods may include selectively removing at least a portion of the exposed silicon-and-oxygen-containing material.

公开(公告)号：US11732352B2

公开(公告)日：2023-08-22

申请号：US17173871

申请日：2021-02-11

Applicant: Applied Materials, Inc.

Inventor： Zeqing Shen ,  Bo Qi ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: C23C16/40 ,  C23C16/52

CPC classification number: C23C16/402 ,  C23C16/52

Abstract: Hydrogen free (low-H) silicon dioxide layers are disclosed. Some embodiments provide methods for forming low-H layers using hydrogen-free silicon precursors and hydrogen-free oxygen sources. Some embodiments provide methods for tuning the stress profile of low-H silicon dioxide films. Further, some embodiments of the disclosure provide oxide-nitride stacks which exhibit reduced stack bow after anneal.

公开(公告)号：US20230157004A1

公开(公告)日：2023-05-18

申请号：US18096923

申请日：2023-01-13

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B12/30 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1222 ,  H01L27/1255 ,  H01L29/6675 ,  H01L29/42392 ,  H01L29/78672 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US20220216058A1

公开(公告)日：2022-07-07

申请号：US17142626

申请日：2021-01-06

Applicant: Applied Materials, Inc.

Inventor： Jialiang Wang ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: H01L21/285 ,  H01L23/532

Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.

公开(公告)号：US20210249415A1

公开(公告)日：2021-08-12

申请号：US17159534

申请日：2021-01-27

Applicant: Applied Materials, Inc.

Inventor： CHANG SEOK KANG ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.